參數(shù)資料
型號(hào): LSI53C810A
英文描述: LSI53C810A PCI to SCSI I/O Processor technical manual v2.1 3/01
中文描述: LSI53C810A的PCI到SCSI I / O處理器技術(shù)手冊(cè)2.1 3 / 01
文件頁數(shù): 19/166頁
文件大?。?/td> 1330K
代理商: LSI53C810A
8051/8032 Background
2-3
Figure 2.1
Internal RAM
External Data Memory Map –
The address decode block in the
LSI53C040 decodes addresses that are generated by the
microcontroller. Additionally, it multiplexes memory space accesses
between the different register and memory blocks according to the
memory map. See
Figure 2.2
for an example of this memory map.
0x7F
Bit Addresses for This
RAM Area Only
0x00
Register
Bank 0
General
Purpose
Area
Bit
Address
Area
Register
Bank 3
Register
Bank 2
Register
Bank 1
R7
R6
R5
R4
R3
R2
R1
R0
0x7F
0x30
0x2F
0x20
0x1F
0x18
0x17
0x10
0x0F
0x08
0x07
0x06
0x05
0x04
0x03
0x02
0x01
0x00
Byte
Addresses
0x80
0xFF
Lower 128 Bytes
Upper 128 Bytes
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