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參數(shù)資料
| 型號： | LS7266R1 |
| 廠商： | LSI Corporation |
| 元件分類： | 通用總線功能 |
| 英文描述： | 24-BIT DUAL-AXIS QUADRATURE COUNTER |
| 中文描述： | 24位雙軸正交計數(shù)器 |
| 文件頁數(shù)： | 2/14頁 |
| 文件大?。?/td> | 71K |
| 代理商： | LS7266R1 |
7
6
5
4
3
2
1
0
BT: Borrow Toggle flip-flop.
Toggles every time CNTR underflows.
CT: Carry toggle flip-flop.
Toggles every time CNTR overflows.
CPT: Compare toggle flip-flop.
Toggles every time PR equals CNTR.
S: Sign flag. Set to1 when CNTR underflows.
Reset to 0 when CNTR overflows.
FLAG
E: Error flag. Set to 1 when excessive noise is present at the count
inputs in quadrature mode. Irrelevant in non-quadrature mode.
U/D: Up/Down flag. Set to 1 when counting up
and reset to 0 when counting down.
Not used. Always reset to 0.
IDX: Index. Set to 1 when selected index input is at active level.
0
:
Filter Clock Prescalers: XPSC and YPSC
Each PSC is an 8-bit programmable modulo-N down counter, driven by the FCK clock. The factor N is down loaded
into a PSC from the associated PR low byte register PR0. The PSCs provide the ability to generate independent filter
clock frequencies for each channel. The PSCs generate the internal filter clock, FCKn used to
validate inputs X
A
, X
B
, Y
A
, Y
B
in the quadrature mode.
Final filter clock frequency f
FCKn
= ( f
FCK
/(n+1) )
,
where n = PSC = 0 to FF
H.
For proper counting in the quadrature
mode, f
FCK
n
≥
8f
QA
(or 8f
QB
), where f
QA
and f
QB
are the clock frequencies at inputs A and B. In non-quadrature mode
filter clock is not needed and the FCK input (Pin 2), should be tied to V
DD
.
7266R1-111196-2
Flag Register: XFLAG and YFLAG
The FLAG registers hold the status information of the CNTRs and can be read out on the data bus. The E bit of a
FLAG register is set to 1 when the noise pulses at the quadrature inputs are wide enough to be validated by the
input filter circuits. E = 1 indicates excessive noise at the inputs but not a definite count error. Once set, E can
only be reset via the RLD.
7
6
5
4
3
2
1
0
0: NOP
1: Reset BP
0
0
1
0
0
1
1
1
0
0
RLD
0
0
0 : Select the RLD addressed by X/Y input
1 : Select both XRLD and YRLD together
(Note: D7 = 1 overrides X/Y input)
: Select RLD
: NOP
: Reset CNTR
: Reset BT, CT, CPT,S
: Reset E
1
0
0
1
1
1
: NOP
: Transfer PR to CNTR
(Note: All 24-bits are transferred in parallel)
: Transfer CNTR to OL
(Note: All 24-bits are transferred in parallel)
: Transfer PR0 to PSC
Reset and Load Signal Decoders: XRLD and YRLD
Following functions can be performed by writing a control byte into an RLD: Transfer PR to CNTR, Transfer
CNTR to OL, reset CNTR, reset FLAG and reset BP
.
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