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參數(shù)資料
| 型號： | LS7266R1 |
| 廠商： | LSI Corporation |
| 元件分類： | 通用總線功能 |
| 英文描述： | 24-BIT DUAL-AXIS QUADRATURE COUNTER |
| 中文描述： | 24位雙軸正交計數(shù)器 |
| 文件頁數(shù)： | 1/14頁 |
| 文件大?。?/td> | 71K |
| 代理商： | LS7266R1 |
24-BIT DUAL-AXIS QUADRATURE COUNTER
LS7266R1 Registers:
LS7266R1 has a set of registers associated with each X and Y axis. All X-axis registers have the name prefix X,
whereas all Y-axis registers have the prefix Y. Selection of a specific register for Read/Write is made from the decode
of the three most significant bits (D7-D5) of the data-bus. CS input enables the IC for Read/Write. C/D input selects
between control and data information for Read/Write. Following is a complete list of LS7266R1 registers.
December 2002
7266R1-121002-1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
YLCNTR/YLOL
FCK
V
DD
(+5V)
D0
D1
D2
D3
D4
D5
D6
D7
V
SS
(GND)
C/D
WR
L
CS
RD
XRCNTR/XABG
XLCNTR/XLOL
XA
XB
XFLG1
YA
YB
YFLG2
YFLG1
YRCNTR/YABG
XFLG2
X/Y
PIN ASSIGNMENT - TOP VIEW
28-Pin Package
Preset Registers: XPR and YPR
Each of these PRs are 24-bit wide. 24-bit data can be written into a PR, one byte at a time, in a sequence of three data
write cycles.
PR
7
7
0
0 7
0
HI BYTE
(PR2)
MID BYTE
(PR1)
LO BYTE
(PR0)
Output Latches: XOL and YOL
Each OL is 24-bits wide. In effect, the OLs are the output ports for the CNTRs. Data from each CNTR can be loaded
into its associated OL and then read back on the data-bus, one byte at a time, in a sequence of three data Read
cycles.
OL
7
7
0
0 7
0
(OL2)
MI(OL1)
(OL0)
Counters: XCNTR and YCNTR
Each of these CNTRs are 24-bit synchronous Up/Down counters. The count clocks for each CNTR is derived from its
associated A/B inputs. Each CNTR can be loaded with the content of its associated PR.
Byte Pointers: XBP and YBP
The Read and Write operations on an OL or a PR always accesses one byte at a time. The byte that is accessed is
addressed by one of the BPs. At the end of every data Read or Write cycle on an OL or a PR, the associated BP is
automatically incremented to address the next byte.
FEATURES:
30 MHz count frequency in non-quadrature mode,
17MHz in x4 quadrature mode.
Dual 24-bit counters to support X and Y axes in
motion control applications.
Dual 24-bit comparators.
Digital filtering of the input quadrature clocks
Programmable 8-bit separate filter clock prescalers
for each axis.
Error flags for noise exceeding filter band width.
Programmable Index Input and other programmable I/Os.
Independent mode programmability for each axis.
Programmable count modes:
Quadrature (x1, x2, x4) / Non-quadrature,
Normal / Modulo-N / Range Limit / Non-Recycle,
Binary / BCD.
8-bit 3-State data I/O bus.
5V operation (V
DD
-V
SS
).
TTL/CMOS compatible I/Os.
LS7266R1 (DIP); LS7266R1-SD (Skinny DIP);
LS7266R1-S (SOIC); LS7266R1-TS (TSSOP)
LSI/CSI
LSI Computer Systems, Inc. 1235 Walt Whitman Road, Melville, NY 11747 (631) 271-0400 FAX (631) 271-0405
LS7266R1
UL
A3800
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