參數(shù)資料
型號(hào): LPC1317FHN33,551
廠商: NXP Semiconductors
文件頁(yè)數(shù): 61/77頁(yè)
文件大?。?/td> 0K
描述: IC MCU 32BIT 64KB FLASH 33HVQFN
標(biāo)準(zhǔn)包裝: 260
系列: LPC13xx
核心處理器: ARM? Cortex?-M3
芯體尺寸: 32-位
速度: 72MHz
連通性: I²C,Microwire,SPI,SSI,SSP,UART/USART
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,POR,WDT
輸入/輸出數(shù): 26
程序存儲(chǔ)器容量: 64KB(64K x 8)
程序存儲(chǔ)器類型: 閃存
EEPROM 大?。?/td> 4K x 8
RAM 容量: 10K x 8
電壓 - 電源 (Vcc/Vdd): 2 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 32-VQFN 裸露焊盤
包裝: 托盤
其它名稱: 568-9599
LPC1315_16_17_45_46_47
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 3 — 20 September 2012
64 of 77
NXP Semiconductors
LPC1315/16/17/45/46/47
32-bit ARM Cortex-M3 microcontroller
12.4 Standard I/O pad configuration
Figure 32 shows the possible pin modes for standard I/O pins with analog input function:
Digital output driver
Digital input: Pull-up enabled/disabled
Digital input: Pull-down enabled/disabled
Digital input: Repeater mode enabled/disabled
Analog input
Fig 32. Standard I/O pad configuration
PIN
VDD
ESD
VSS
ESD
strong
pull-up
strong
pull-down
VDD
weak
pull-up
weak
pull-down
open-drain enable
output enable
repeater mode
enable
pull-up enable
pull-down enable
select data
inverter
data output
data input
select glitch
filter
analog input
select analog input
002aaf695
pin configured
as digital output
driver
pin configured
as digital input
pin configured
as analog input
10 ns RC
GLITCH FILTER
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