參數資料
型號： LPC1317FHN33,551
廠商： NXP Semiconductors
文件頁數： 37/77頁
文件大?。?/td> 0K
描述： IC MCU 32BIT 64KB FLASH 33HVQFN
標準包裝： 260
系列： LPC13xx
核心處理器： ARM? Cortex?-M3
芯體尺寸： 32-位
速度： 72MHz
連通性： I²C，Microwire，SPI，SSI，SSP，UART/USART
外圍設備： 欠壓檢測/復位，POR，WDT
輸入/輸出數： 26
程序存儲器容量： 64KB（64K x 8）
程序存儲器類型： 閃存
EEPROM 大小： 4K x 8
RAM 容量： 10K x 8
電壓 - 電源 (Vcc/Vdd)： 2 V ~ 3.6 V
數據轉換器： A/D 8x12b
振蕩器型： 內部
工作溫度： -40°C ~ 85°C
封裝/外殼： 32-VQFN 裸露焊盤
包裝： 托盤
其它名稱： 568-9599
LPC1315_16_17_45_46_47
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 3 — 20 September 2012
42 of 77
NXP Semiconductors
LPC1315/16/17/45/46/47
32-bit ARM Cortex-M3 microcontroller
[3]
System oscillator enabled; PLL and IRC disabled.
[4]
IRC enabled; system oscillator disabled; system PLL disabled.
[5]
IDD measurements were performed with all pins configured as GPIO outputs driven LOW and pull-up resistors disabled.
[6]
BOD disabled.
[7]
All peripherals disabled in the AHBCLKCTRL register. Peripheral clocks to USART, SSP0/1 disabled in the syscon block.
[8]
USB_DP and USB_DM pulled LOW externally.
[9]
Low-current mode PWR_LOW_CURRENT selected when running the set_power routine in the power profiles.
[10] IRC disabled; system oscillator enabled; system PLL enabled.
[11] WAKEUP pin pulled HIGH externally. An external pull-up resistor is required on the RESET pin for the Deep power-down mode.
[12] Including voltage on outputs in 3-state mode.
[13] VDD supply voltage must be present.
[14] 3-state outputs go into 3-state mode in Deep power-down mode.
[15] Allowed as long as the current limit does not exceed the maximum current allowed by the device.
[16] To VSS.
[17] Includes external resistors of 33
1 % on USB_DP and USB_DM.
9.1 BOD static characteristics
[1]
Interrupt levels are selected by writing the level value to the BOD control register BODCTRL, see
LPC1315/16/17/45/46/47 user manual.
Table 7.
BOD static characteristics[1]
Tamb =25 C.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Vth
threshold voltage
interrupt level 1
assertion
-
2.22
-
V
de-assertion
-
2.35
-
V
interrupt level 2
assertion
-
2.52
-
V
de-assertion
-
2.66
-
V
interrupt level 3
assertion
-
2.80
-
V
de-assertion
-
2.90
-
V
reset level 0
assertion
-
1.46
-
V
de-assertion
-
1.63
-
V
reset level 1
assertion
-
2.06
-
V
de-assertion
-
2.15
-
V
reset level 2
assertion
-
2.35
-
V
de-assertion
-
2.43
-
V
reset level 3
assertion
-
2.63
-
V
de-assertion
-
2.71
-
V
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