參數(shù)資料
型號: LPC1317FHN33,551
廠商: NXP Semiconductors
文件頁數(shù): 5/77頁
文件大?。?/td> 0K
描述: IC MCU 32BIT 64KB FLASH 33HVQFN
標準包裝: 260
系列: LPC13xx
核心處理器: ARM? Cortex?-M3
芯體尺寸: 32-位
速度: 72MHz
連通性: I²C,Microwire,SPI,SSI,SSP,UART/USART
外圍設備: 欠壓檢測/復位,POR,WDT
輸入/輸出數(shù): 26
程序存儲器容量: 64KB(64K x 8)
程序存儲器類型: 閃存
EEPROM 大小: 4K x 8
RAM 容量: 10K x 8
電壓 - 電源 (Vcc/Vdd): 2 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 32-VQFN 裸露焊盤
包裝: 托盤
其它名稱: 568-9599
LPC1315_16_17_45_46_47
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 3 — 20 September 2012
13 of 77
NXP Semiconductors
LPC1315/16/17/45/46/47
32-bit ARM Cortex-M3 microcontroller
SWCLK/PIO0_10/SCK0/
CT16B0_MAT2
38
29
19
I; PU
I
SWCLK — Serial wire clock and test clock TCK for JTAG
interface.
-I/O
PIO0_10 — General purpose digital input/output pin.
-O
SCK0 — Serial clock for SSP0.
-O
CT16B0_MAT2 — Match output 2 for 16-bit timer 0.
TDI/PIO0_11/AD0/
CT32B0_MAT3
42
32
21
I; PU
I
TDI — Test Data In for JTAG interface.
-I/O
PIO0_11 — General purpose digital input/output pin.
-I
AD0 — A/D converter, input 0.
-O
CT32B0_MAT3 — Match output 3 for 32-bit timer 0.
TMS/PIO0_12/AD1/
CT32B1_CAP0
44
33
22
I; PU
I
TMS — Test Mode Select for JTAG interface.
-I/O
PIO_12 — General purpose digital input/output pin.
-I
AD1 — A/D converter, input 1.
-I
CT32B1_CAP0 — Capture input 0 for 32-bit timer 1.
TDO/PIO0_13/AD2/
CT32B1_MAT0
45
34
23
I; PU
O
TDO — Test Data Out for JTAG interface.
-I/O
PIO0_13 — General purpose digital input/output pin.
-I
AD2 — A/D converter, input 2.
-O
CT32B1_MAT0 — Match output 0 for 32-bit timer 1.
TRST/PIO0_14/AD3/
CT32B1_MAT1
46
35
24
I; PU
I
TRST — Test Reset for JTAG interface.
-I/O
PIO0_14 — General purpose digital input/output pin.
-I
AD3 — A/D converter, input 3.
-O
CT32B1_MAT1 — Match output 1 for 32-bit timer 1.
SWDIO/PIO0_15/AD4/
CT32B1_MAT2
52
39
25
I; PU
I/O
SWDIO — Serial wire debug input/output.
-I/O
PIO0_15 — General purpose digital input/output pin.
-I
AD4 — A/D converter, input 4.
-O
CT32B1_MAT2 — Match output 2 for 32-bit timer 1.
PIO0_16/AD5/
CT32B1_MAT3/WAKEUP
53
40
26
I; PU
I/O
PIO0_16 — General purpose digital input/output pin.
-I
AD5 — A/D converter, input 5.
-O
CT32B1_MAT3 — Match output 3 for 32-bit timer 1.
-I
WAKEUP — Deep power-down mode wake-up pin with
20 ns glitch filter. This pin must be pulled HIGH externally
to enter Deep power-down mode and pulled LOW to exit
Deep power-down mode. A LOW-going pulse as short as
50 ns wakes up the part.
PIO0_17/RTS/
CT32B0_CAP0/SCLK
60
45
30
I; PU
I/O
PIO0_17 — General purpose digital input/output pin.
-O
RTS — Request To Send output for USART.
-I
CT32B0_CAP0 — Capture input 0 for 32-bit timer 0.
-I/O
SCLK — Serial clock input/output for USART in
synchronous mode.
Table 3.
Pin description (LPC1315/16/17 - no USB)
Symbol
LQ
FP6
4
LQ
FP4
8
HVQFN
3
Re
set
st
ate
[1
]
Ty
p
e
Description
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