參數(shù)資料
型號: LPC1317FHN33,551
廠商: NXP Semiconductors
文件頁數(shù): 42/77頁
文件大?。?/td> 0K
描述: IC MCU 32BIT 64KB FLASH 33HVQFN
標(biāo)準(zhǔn)包裝: 260
系列: LPC13xx
核心處理器: ARM? Cortex?-M3
芯體尺寸: 32-位
速度: 72MHz
連通性: I²C,Microwire,SPI,SSI,SSP,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,WDT
輸入/輸出數(shù): 26
程序存儲器容量: 64KB(64K x 8)
程序存儲器類型: 閃存
EEPROM 大小: 4K x 8
RAM 容量: 10K x 8
電壓 - 電源 (Vcc/Vdd): 2 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 32-VQFN 裸露焊盤
包裝: 托盤
其它名稱: 568-9599
LPC1315_16_17_45_46_47
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 3 — 20 September 2012
47 of 77
NXP Semiconductors
LPC1315/16/17/45/46/47
32-bit ARM Cortex-M3 microcontroller
9.3 Electrical pin characteristics
ROM
-
0.04
0.15
0.22
SSP0
-
0.11
0.41
0.60
SSP1
-
0.11
0.41
0.60
USART
-
0.20
0.76
1.11
WDT
-
0.01
0.05
0.08
Main clock selected as clock source for the WDT.
USB
-
1.2
-
Table 8.
Power consumption for individual analog and digital blocks
The supply current per peripheral is measured as the difference in supply current between the peripheral block enabled and
the peripheral block disabled in the SYSAHBCLKCTRL or PDRUNCFG (for analog blocks) registers. All other blocks are
disabled in both registers and no code is executed. Measured on a typical sample at Tamb =25 C. Unless noted otherwise,
the system oscillator and PLL are running in both measurements.
Typical supply current per peripheral
in mA for different system clock
frequencies
Notes
n/a
12 MHz
48 MHz
72 MHz
Conditions: VDD = 3.3 V; on pin PIO0_7.
Fig 16. High-drive output: Typical HIGH-level output voltage VOH versus HIGH-level
output current IOH.
IOH (mA)
0
60
40
20
10
50
30
002aae990
2.8
2.4
3.2
3.6
VOH
(V)
2
T = 85
°C
25
°C
40 °C
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