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參數(shù)資料
| 型號： | LMX2331A |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | PLLatinum⑩ Dual Frequency Synthesizer for RF Personal Communications |
| 中文描述： | PLLatinum⑩雙頻率合成射頻個人通信 |
| 文件頁數(shù)： | 12/17頁 |
| 文件大小： | 392K |
| 代理商： | LMX2331A |
Functional Description
(Continued)
TABLE 1. Programmable Modes
C1
C2
R16
R17
R18
IF D
o
R19
R20
0
0
IF Phase
Detector Polarity
RF Phase
Detector Polarity
IF I
CP
o
TRI-STATE
RF D
o
TRI-STATE
IF LD
IF F
o
0
1
RF I
CP
o
RF LD
RF F
o
C1
1
1
C2
0
1
N19
N20
IF Prescaler
RF Prescaler
Pwdn IF
Pwdn RF
TABLE 2. Mode Select Truth Table
Phase Detector Polarity
D
o
TRI-STATE
I
CP
o
(Note 6)
IF
Prescaler
2330A RF
Prescaler
2331A/32A RF
Prescaler
Pwdn
(Note 7)
Pwrd
Up
Pwrd
Dn
0
Negative
Normal
Operation
LOW
8/9
32/33
64/65
1
Positive
TRI-STATE
HIGH
16/17
64/65
128/129
Note 6:
The I
CPo
LOW current state = 1/4 x I
CPo
HIGH current.
Note 7:
Activation of the IF PLL or RF PLL powerdown modes result in the disabling of the respective N counter divider and debiasing of its respective f
inputs
(to a high impedance state). The powerdown function is gated by the charge pump to prevent unwanted frequency jumps. Once the powerdown program mode is
loaded, the part will go into powerdown mode when the charge pump reaches a TRI-STATE condition. The R counter functionality does not become disabled until
bothIF and RF powerdown bits are activated. The MICROWIRE control register remains active and capable of loading and latching data during all of the powerdown
modes.
TABLE 3. The F
o
LD (Pin 10) Output Truth Table
RF R[19]
(RF LD)
0
0
1
1
X
X
X
X
0
0
1
1
IF R[19]
(IF LD)
0
1
0
1
0
0
1
1
0
1
0
1
RF R[20]
(RF F
o
)
0
0
0
0
0
1
0
1
1
1
1
1
IF R[20]
(IF F
o
)
0
0
0
0
1
0
1
0
1
1
1
1
F
o
Output State
Disabled (Note 8)
IF Lock Detect (Note 9)
RF Lock Detect (Note 9)
RF/IF Lock Detect (Note 9)
IF Reference Divider Output
RF Reference Divider Output
IF Programmable Divider Output
RF Programmable Divider Output
Fastlock (Note 10)
For Internal Use Only
For Internal Use Only
Counter Reset (Note 11)
X = don’t care condition
Note 8:
When the F
o
LD output is disabled, it is actively pulled to a low logic state.
Note 9:
Lock detect output provided to indicate when the VCO frequency is in “l(fā)ock.” When the loop is locked and a lock detect mode is selected, the pins output
is HIGH, with narrow pulses LOW. In the RF/IF lock detect mode a locked condition is indicated when RF and IF are both locked.
Note 10:
The Fastlock mode utilizes the F
LD output pin to switch a second loop filter damping resistor to ground during fastlock operation. Activation of Fastlock
occurs whenever the RF loop’s lcpo magnitude bit
#
17 is selected HIGH (while the
#
19 and
#
20 mode bits are set for Fastlock).
Note 11:
The Counter Reset mode bits R19 and R20 when activated reset all counters. Upon removal of the Reset bits then N counter resumes counting in “close”
alignment with the R counter. (The maximum error is one prescaler cycle.) If the Reset bits are activated the R counter is also forced to Reset, allowing smooth ac-
quisition upon powering up.
www.national.com
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LMX2331ATM | 制造商:Texas Instruments 功能描述: |
| LMX2331ATMX | 功能描述:IC FREQ SYNTH DUAL 20-TSSOP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:PLLatinum™ 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| LMX2331L | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| LMX2331LSLB | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:PLLatinum⑩ Low Power Dual Frequency Synthesizer for RF Personal Communications |
| LMX2331LSLBX | 制造商:Texas Instruments 功能描述: |
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