參數(shù)資料
型號(hào): LMX2331A
廠商: National Semiconductor Corporation
英文描述: PLLatinum⑩ Dual Frequency Synthesizer for RF Personal Communications
中文描述: PLLatinum⑩雙頻率合成射頻個(gè)人通信
文件頁(yè)數(shù): 10/17頁(yè)
文件大小: 392K
代理商: LMX2331A
Functional Description
The simplified block diagram below shows the 22-bit data register, two 15-bit R Counters and the 15- and 18-bit N Counters (in-
termediate latches are not shown). The data stream is clocked (on the rising edge of Clock) into the DATA register, MSB first. The
data stored in the shift register is loaded into one of 4 appropriate latches on the rising edge of LE. The last two bits are the Con-
trol Bits. The DATA is transferred into the counters as follows:
Control Bits
C1
0
0
1
1
DATA Location
C2
0
1
0
1
IF R Counter
RF R Counter
IF N Counter
RF N Counter
PROGRAMMABLE REFERENCE DIVIDERS (IF AND RF R COUNTERS)
If the Control Bits are 00 or 01 (00 for IF and 01 for RF) data is transferred from the 22-bit shift register into a latch which sets
the 15-bit R Counter. Serial data format is shown below.
15-BIT PROGRAMMABLE REFERENCE DIVIDER RATIO (R COUNTER)
Divide
Ratio
3
4
32767
R
15
0
0
1
R
14
0
0
1
R
13
0
0
1
R
12
0
0
1
R
11
0
0
1
R
10
0
0
1
R
9
0
0
1
R
8
0 0 0 0 0 0 1 1
0 0 0 0 0 1 0 0
1 1 1 1 1 1 1 1
R
7
R
6
R
5
R
4
R
3
R
2
R
1
Notes:
Divide ratios less than 3 are prohibited.
Divide ratio: 3 to 32767
R1 to R15: These bits select the divide ratio of the programmable reference divider.
Data is shifted in MSB first.
DS012331-1
DS012331-14
www.national.com
10
相關(guān)PDF資料
PDF描述
LMX2331 PLLatinum⑩ Low Power Dual Frequency Synthesizer for RF Personal Communications
LMX2331LTM PLLatinum⑩ Low Power Dual Frequency Synthesizer for RF Personal Communications
LMX2331LSLB PLLatinum⑩ Low Power Dual Frequency Synthesizer for RF Personal Communications
LMX2335UTMX PLLatinum Ultra Low Power Dual Frequency Synthesizer for RF Personal Communications
LMX2335USLBX PLLatinum Ultra Low Power Dual Frequency Synthesizer for RF Personal Communications
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