(C0 + CL1) - 1 " />
參數(shù)資料
型號： LMK04033BEVAL/NOPB
廠商： National Semiconductor
文件頁數(shù)： 44/65頁
文件大小： 0K
描述： BOARD EVALUATION LMK04033
標準包裝： 1
系列： PowerWise®
主要目的： 計時，時鐘調節(jié)器
嵌入式： 否
已用 IC / 零件： LMK04033
主要屬性： LVPECL、2VPECL、LVDS 和 LVCMOS 輸出
次要屬性： 集成式 PLL 和 VCO
已供物品： 板，線纜，文檔
1
(C0 + CL1)
-
1
(C0 + CL2)
=
2
1
FFCL1
FCL1 - FCL2
=
2
C1
=
F
'F
C0
C1
¨
§
CL2
C1
+
1
-
C0
C1
¨
§
CL1
C1
+
1
2(C0 + CL1)
+ 1
C0
C1
¨
§
CL
C1
+
1
+ 1
2
C1
FL = FS
= FS
SNOSAZ8J – SEPTEMBER 2008 – REVISED SEPTEMBER 2011
The 2.2 nF capacitors shown in the circuit are coupling capacitors that block the DC tuning voltage applied by the
4.7 k and 10 k resistors. The value of these coupling capacitors should be large, relative to the value of CTUNE
(CC1 = CC2 >> CTUNE), so that CTUNE becomes the dominant capacitance.
For a specific value of CL, the corresponding resonant frequency (FL) of the parallel resonant mode circuit is:
FS = Series resonant frequency
C1 = Motional capacitance of the crystal
CL = Load capacitance
C0 = Shunt capacitance of the crystal, specified on the crystal datasheet
The normalized tuning range of the circuit is closely approximated by:
CL1, CL2 = The endpoints of the circuit’s load capacitance range, assuming a variable capacitance element is one
component of the load. FCL1, FCL2 = parallel resonant frequencies at the extremes of the circuit’s load
capacitance range.
A common range for the pullability ratio, C0/C1, is 250 to 280. The ratio of the load capacitance to the shunt
capacitance is ~(n * 1000), n < 10. Hence, picking a crystal with a smaller pullability ratio supports a wider tuning
range because this allows the scale factors related to the load capacitance to dominate.
Examples of the phase noise and jitter performance of the LMK04031 with a crystal oscillator are shown in
Table 34. This table illustrates the clock output phase noise when a 12.288 MHz crystal is paired with PLL1.
Table 34. Example RMS Jitter and Clock Output Phase Noise for LMK04031 with a
12.288 MHz Crystal Driving OSCin (T = 25 °C, VCC = 3.3 V)
(1)
RMS Jitter (ps)
Integration Bandwidth
Clock Output Type
PLL2 PDF = 12.288 MHz
PLL2 PDF = 24.576 MHz
(EN_PLL2_REF2X = 0)
(EN_PLL2_REF2X = 1)
FCLK = 122.88 MHz
FCLK = 153.6 MHz
FCLK = 122.88 MHz
100 Hz – 20 MHz
LVPECL
0.279
0.263
0.300
LVCMOS
0.244
0.248
0.218
LVDS
0.272
0.269
0.245
10 kHz – 20 MHz
LVPECL
0.251
0.234
0.284
LVCMOS
0.211
0.215
0.193
LVDS
0.236
0.235
0.217
Phase Noise (dBc/Hz)
Offset
Clock Output Type
PLL2 FPD = 12.288 MHz
PLL2 FPD = 24.576 MHz
(EN_PLL2_REF2X = 0)
(EN_PLL2_REF2X = 1)
FCLK = 122.88 MHz
FCLK = 153.6 MHz
FCLK = 122.88 MHz
100 Hz
LVPECL
-107
-106
LVCMOS
-105
-103
-104
LVDS
-105
-104
-106
(1)
Performance data and crystal specifications contained in this section are based on Ecliptek model ECX-6465, 12.288 MHz.
Copyright 2008–2011, Texas Instruments Incorporated
49
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