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參數(shù)資料
| 型號： | LMK04033BEVAL/NOPB |
| 廠商： | National Semiconductor |
| 文件頁數(shù)： | 18/65頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION LMK04033 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | PowerWise® |
| 主要目的： | 計時，時鐘調(diào)節(jié)器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | LMK04033 |
| 主要屬性： | LVPECL、2VPECL、LVDS 和 LVCMOS 輸出 |
| 次要屬性： | 集成式 PLL 和 VCO |
| 已供物品： | 板，線纜，文檔 |
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Distribution
Path
SYNC*
CLKout0
CLKout1
CLKout2
SNOSAZ8J – SEPTEMBER 2008 – REVISED SEPTEMBER 2011
Global Clock Output Synchronization (Sync*)
The SYNC* input is used to synchronize the active clock outputs. When SYNC* is held in a logic low state, the
outputs are also held in a logic low state. When SYNC* goes high, the clock outputs are activated and will
transition to a high state simultaneously with one another.
SYNC* must be held low for greater than one clock cycle of the Clock Distribution Path. After this low event has
been registered, the outputs will not reflect the low state for four more cycles. Similarly after SYNC* becomes
high, the outputs will simultaneously transition high after four Clock Distribution Path cycles have passed. See
Figure 11 for further detail.
Figure 11. Clock Output synchronization using the SYNC* pin
Global Output Enable and Lock Detect
Each Clock Output Channel may be either enabled or put into a high impedance state via the Clock Output
Enable control bit (one for each channel). Each output enable control bit is gated with the Global Output Enable
input pin (GOE). The GOE pin provides an internal pull-up so that if it is un-terminated externally, then the clock
output states are determined by the Clock Channel Output Enable Register bits. All clock outputs can be
disabled simultaneously if the GOE pin is pulled low by an external signal.
Table 2. Clock Output Control
CLKoutX
EN_CLKout
CLKoutX Output State
GOE pin
_EN bit
_Global bit
1
Low
Don't care
0
Don't care
Off
0
Don't care
Off
1
High / No Connect
Enabled
The Lock Detect (LD) signal can be connected to the GOE pin in which case all outputs are disabled
automatically if the synthesizer is not locked. See EN_CLKoutX: Clock Channel Output Enable and also System
Level Diagram for actual implementation details.
The Lock Detect (LD) pin can be programmed to output a ‘High’ when both PLL1 and PLL2 are locked, or only
when PLL1 is locked or only when PLL2 is locked.
FUNCTIONAL DESCRIPTION
Architectural Overview
The LMK040xx chip consists of two high performance synthesizer blocks (Phase Locked Loop, internal
VCO/VCO Divider, and loop filter), source selection, distribution system, and independent clock output channels.
The Phase Frequency Detector in PLL1 compares the divided (R Divider 1) system clock signal from the
selected CLKinX and CLKinX* input with the divided (N Divider 1) output of the external VCXO attached to the
PLL2 OSCin port. The external loop filter for PLL1 should be narrow to provide an ultra clean reference clock
from the external VCXO to the OSCin/OSCin* pins for PLL2.
Copyright 2008–2011, Texas Instruments Incorporated
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| LMK04033BISQ | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Low-Noise Clock Jitter Cleaner with Cascaded PLLs |
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