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參數(shù)資料
| 型號： | LMK04033BEVAL/NOPB |
| 廠商： | National Semiconductor |
| 文件頁數(shù)： | 39/65頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION LMK04033 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | PowerWise® |
| 主要目的： | 計時，時鐘調(diào)節(jié)器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | LMK04033 |
| 主要屬性： | LVPECL、2VPECL、LVDS 和 LVCMOS 輸出 |
| 次要屬性： | 集成式 PLL 和 VCO |
| 已供物品： | 板，線纜，文檔 |
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SNOSAZ8J – SEPTEMBER 2008 – REVISED SEPTEMBER 2011
The loop filter for PLL2 consists of three external components that implement two lower order poles, plus optional
internal integrated components if 3rd or 4th order poles are needed. The loop filter components for PLL1 must be
external components.
The VCO output buffer signal that appears at the Fout pin when enabled (EN_Fout = 1) should be AC coupled
using a 100 pF capacitor. This output is a single-ended signal by default. If a differential signal is required, a 50
Ω balun may be connected to this pin to convert it to differential.
The clock outputs are all AC coupled with 0.1 F capacitors. CLKout1 and CLKout3 are depicted as LVPECL,
with 120
Ω emitter resistors as source termination. However, the output format of the clock channels will vary by
device part number, so the designer should use the appropriate source termination for each channel. Later
sections of this data sheet illustrate alternative methods for AC coupling, DC coupling and terminating the clock
outputs.
LDO Bypass And Bias Pin
The LDObyp1 and LDObyp2 pins should be connected to GND through external capacitors, as shown in the
diagram. Furthermore, the Bias pin should be connected to VCC through a 1 F capacitor in series.
Loop Filter
Each PLL of the LMK04000 family requires a dedicated loop filter. The loop filter for PLL1 must be connected to
the CPout1 pin. Figure 14 shows a simple 2-pole loop filter. The output of the filter drives an external VCXO
module or discrete implementation of a VCXO using a crystal resonator. Higher order loop filters may be
implemented using additional external R and C components. It is recommended the loop filter for PLL1 result in a
total closed loop bandwidth in the range of 10 Hz to 200 Hz. The design of the loop filter is application specific
and highly dependent on parameters such as the phase noise of the reference clock, VCXO phase noise, and
phase detector frequency for PLL1. National’s Clock Conditioner Owner’s Manual covers this topic in detail and
National’s Clock Design Tool can be used to simulate loop filter designs for both PLLs. These resources may be
As shown in the diagram, the charge pump for PLL2 is directly connected to the optional internal loop filter
components, which are normally used only if either a third or fourth pole is needed. The first and second poles
are implemented with external components. The loop must be designed to be stable over the entire application-
specific tuning range of the VCO. The designer should note the range of KVCO listed in the table of Electrical
Characteristics and how this value can change over the expected range of VCO tuning frequencies. Because
loop bandwidth is directly proportional to KVCO, the designer should model and simulate the loop at the expected
extremes of the desired tuning range, using the appropriate values for KVCO.
When designing with the integrated loop filter of the LMK04000 family, considerations for minimum resistor
thermal noise often lead one to the decision to design for the minimum value for integrated resistors, R3 and R4.
Both the integrated loop filter resistors and capacitors (C3 and C4) also restrict the maximum loop bandwidth.
However, these integrated components do have the advantage that they are closer to the VCO and can therefore
filter out some noise and spurs better than external components. For this reason, a common strategy is to
minimize the internal loop filter resistors and then design for the largest internal capacitor values that permit a
wide enough loop bandwidth. In situations where spurs requirements are very stringent and there is margin on
phase noise, it might make sense to design for a loop filter with integrated resistor values larger than their
minimum value.
44
Copyright 2008–2011, Texas Instruments Incorporated
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| LMK04033BISQ | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Low-Noise Clock Jitter Cleaner with Cascaded PLLs |
| LMK04033BISQ/NOPB | 功能描述:時鐘合成器/抖動清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| LMK04033BISQE | 制造商:Texas Instruments 功能描述:Clock Conditioner 48-Pin LLP EP T/R 制造商:Texas Instruments 功能描述:PRECISION CLOCK CONDITIONER, 48LLP |
| LMK04033BISQE/NOPB | 功能描述:時鐘合成器/抖動清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| LMK04033BISQX | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Low-Noise Clock Jitter Cleaner with Cascaded PLLs |
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