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參數(shù)資料
| 型號(hào)： | LMK04033BEVAL/NOPB |
| 廠商： | National Semiconductor |
| 文件頁數(shù)： | 38/65頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION LMK04033 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | PowerWise® |
| 主要目的： | 計(jì)時(shí)，時(shí)鐘調(diào)節(jié)器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | LMK04033 |
| 主要屬性： | LVPECL、2VPECL、LVDS 和 LVCMOS 輸出 |
| 次要屬性： | 集成式 PLL 和 VCO |
| 已供物品： | 板，線纜，文檔 |
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C
Po
u
t1
LEuWire
CLKuWire
DATAuWire
GOE
LD
(optional)
To Host
C
L
Ko
u
t0
C
L
Ko
u
t0
*
C
L
Ko
u
t1
*
C
L
Ko
u
t1
C
L
Ko
u
t2
B
C
L
Ko
u
t2
A
C
L
Ko
u
t3
*
C
L
Ko
u
t3
C
L
Ko
u
t4
*
C
L
Ko
u
t4
To
System
SYNC*
C
L
Ki
n
0
C
L
Ki
n
0
*
Bias
Vcc
LDObyp1
LDObyp2
10 PF
0.1 PF
1 PF
0.1 PF
LMK040xx
100
VCXO
OSCin
OSCin*
100
0.1 uF
CLKin1*
CLKin1
0.1 PF
To
System
To Host
CPout2
100 pF
To
System
Fout
Reference Clock #1
(Primary)
Reference Clock #2
(Secondary)
PLL1 Loop Filter
PLL2 Loop Filter
Rterm
0.1 PF
120
120
To
System
To
System
51
0.1 PF
120
120
To
System
0.47 PF
D
L
D
_
BYP
3
p
F
3
p
F
3
p
F
0.1 PF
SNOSAZ8J – SEPTEMBER 2008 – REVISED SEPTEMBER 2011
APPLICATION INFORMATION
System Level Diagram
The following diagram illustrates the typical interconnection of the LMK040xx in a clocking application.
Figure 13. Typical Application
Figure 13 shows an LMK04000 family device with external circuitry. The primary reference clock input is at
CLKin0/0*. A secondary reference clock is driving CLKin1/1*. Both clocks are depicted as AC coupled differential
drivers. The VCXO attached to the OSCin/OSCin* port is configured as an AC coupled single-ended driver. Any
of the input ports (CLKin0/0*, CLKin1/1*, or OSCin/OSCin*) may be configured as either differential or single-
ended. These options are discussed later in the data sheet.
The diagram shows an optional connection between the LD pin and GOE. With this arrangement, the LD pin can
be programmed to output a lock detect signal that is active HIGH (see Table 29 for optional LD pin outputs). If
lock is lost, the LD pin will transition to a LOW, pulling GOE low and causing all clock outputs to be disabled.
This scheme should be used only if disabling the clock outputs is desirable when lock is lost.
Copyright 2008–2011, Texas Instruments Incorporated
43
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LMK04033BISQ | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Low-Noise Clock Jitter Cleaner with Cascaded PLLs |
| LMK04033BISQ/NOPB | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| LMK04033BISQE | 制造商:Texas Instruments 功能描述:Clock Conditioner 48-Pin LLP EP T/R 制造商:Texas Instruments 功能描述:PRECISION CLOCK CONDITIONER, 48LLP |
| LMK04033BISQE/NOPB | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| LMK04033BISQX | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Low-Noise Clock Jitter Cleaner with Cascaded PLLs |
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