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參數資料
| 型號： | LM98501CCVBH |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 消費家電 |
| 英文描述： | 10-Bit, 27 MSPS Camera Signal Processor |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP48 |
| 封裝： | LQFP-48 |
| 文件頁數： | 4/24頁 |
| 文件大?。?/td> | 490K |
| 代理商： | LM98501CCVBH |
Pin Descriptions
(Continued)
Pin
11
Name
DV+
I/O
Typ
P
Description
+3V power supply for the digital circuits. Bypass each supply pin with 0.1 μF and
10 μF capacitors in parallel.
27 MHz clock input.
Correlated double sampler reset voltage clamp override. Programmable active-high or
active-low through serial interface. Connect to +3V digital supply when function not
being used (register values in default condition).
Correlated double sampler video signal voltage sample override. Programmable
active-high or active-low through serial interface. Connect to +3V digital supply when
function not being used (register values in default condition).
Active-high beginning of line switch input. Hold high during entire line of effective
pixels. Hold low during blanking period.
Active-high black level clamp switch input. Pulse high during black pixels to eliminate
black pixel offset from video signal.
Top of DAC reference ladder. Normally bypassed with a 0.1 μF capacitor. An external
DAC reference voltage may be applied to this pin.
Bottom of DAC reference ladder. Normally bypassed with a 0.1 μF capacitor. An
external DAC reference voltage may be applied to this pin.
Bottom of ADC reference ladder. Normally bypassed with a 0.1 μF capacitor. An
external ADC reference voltage may be applied to this pin.
Active-low chip enable for the serial interface.
Serial interface clock used to decode the serial input data.
Serial interface input port.
Serial interface output port.
Digital output driver ground return.
+3V power supply for the digital output driver circuits. Bypass each supply pin with
0.1 μF and 10 μF capacitors in parallel.
Digital output. Bit 0 of 9 (LSB) of the digital video output bus.
Digital output. Bit 1 of 9 of the digital video output bus.
Digital output. Bit 2 of 9 of the digital video output bus.
Digital output. Bit 3 of 9 of the digital video output bus.
Digital output. Bit 4 of 9 of the digital video output bus.
Digital output. Bit 5 of 9 of the digital video output bus.
Digital output. Bit 6 of 9 of the digital video output bus.
Digital output. Bit 7 of 9 of the digital video output bus.
Digital output. Bit 8 of 9 of the digital video output bus.
Digital output. Bit 9 of 9 (MSB) of the digital video output bus.
+3V power supply for the digital output driver circuits. Bypass each supply pin with
0.1 μF and 10 μF capacitors in parallel.
Digital output driver ground return.
Digital ground return.
+3V power supply for the digital circuits. Bypass each supply pin with 0.1 μF and 10
μF capacitors in parallel.
+3V power supply for the analog circuits. Bypass each supply pin with 0.1 μF and 10
μF capacitors in parallel.
Analog ground return.
Top of ADC reference ladder. Normally bypassed with a 0.1 μF capacitor. An external
ADC reference voltage may be applied to this pin.
+3V power supply for the analog circuits. Bypass each supply pin with 0.1 μF and 10
μF capacitors in parallel.
Analog ground return.
Negative differential analog output from correlated double sampler or PGA (selectable
through the serial interface).
12
13
CLK
SHP
I
I
D
D
14
SHD
I
D
15
BOL
I
D
16
BLKCLP
I
D
17
V
REFP
IO
A
18
V
REFN
IO
A
19
V
REFB
IO
A
20
21
22
23
24
25
CE
SCLK
SI DATA
SO DATA
DGND I/O
DV+ I/O
I
I
I
D
D
D
D
P
P
O
26
27
28
29
30
31
32
33
34
35
36
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DV+ I/O
O
O
O
O
O
O
O
O
O
O
D
D
D
D
D
D
D
D
D
D
P
37
38
39
DGND I/O
DGND
DV+
P
P
P
40
AV+
P
41
42
AGND
V
REFT
P
A
IO
43
AV+
P
44
45
AGND
AOUT
P
A
O
L
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