參數(shù)資料
型號(hào)： LM98501CCVBH
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： 消費(fèi)家電
英文描述： 10-Bit, 27 MSPS Camera Signal Processor
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP48
封裝： LQFP-48
文件頁(yè)數(shù)： 19/24頁(yè)
文件大?。?/td> 490K
代理商： LM98501CCVBH
Register Data
(Continued)
Bit
[3]
Bit Symbol
Offset
Auto-Calibration
Enable
Description
Enables the digital black
level correction loop. Analog
offset registers are read-only
when offset auto-calibration
is enabled.
Inverts the SHP and SHD
inputs causing the CDS to
sample on the rising edges
of SHP and SHD. Sampling
is performed on the falling
edges of SHP and SHD
when the signals are
Active-low.
Instructs the CDS to sample
the CCD input. Otherwise,
the AUX In input is sampled
in sample-and-hold mode.
Cuts power to the on-chip
analog circuitry including the
CDS, PGA, ADC, and
bandgap references.
[2]
SHP/SHD
Active-HIGH
Enable
[1]
CDS Enable
(AUX-In
Disable)
[0]
Analog Power
Down
Register Name Software Control 1 (Customer)
Address
D Hex
Type
Read/Write
Reset Value
XX00 0X00 Binary
Bit
[5:4]
Bit Symbol
Analog Output
Select
Description
Routes the selected internal
analog signal to the
differential analog output
pins AOUT+ and AOUT.
00 CDS
01 PGA Stage 1
10 PGA Stage 2
11 PGA Stage 3
Enables the differential
analog output pins AOUT+
and AOUT. If the analog
outputs are disabled, the
pins should not be loaded.
Reference biasing selection
for the analog-to-digital
converter.
0 Passive Biasing
(Resistors)
1 Active Biasing
(Bandgap)
Reference biasing selection
for the digital-to-analog
converter.
0 Active Biasing
(Bandgap)
1 Passive Biasing
(Resistors)
[3]
Analog Output
Enable
[1]
ADC Reference
Select
[0]
DAC Reference
Select
Register Name Power Level Control 0
Address
E Hex
Type
Read/Write
Reset Value
1010 1010 Binary
Bit
[7:6]
Bit Symbol
PGA Stage 1
Amplifier Bias
Description
Adjusts the power level of
the PGA stage 1 amplifier.
The power level is relative to
the value of the binary
number stored.
Adjusts the power level of
the PGA common-mode
input. The power level is
relative to the value of the
binary number stored.
Adjusts the power level of
the CDS amplifier. The
power level is relative to the
value of the binary number
stored.
Adjusts the power level of
the CDS common-mode
input. The power level is
relative to the value of the
binary number stored.
[5:4]
PGA
Common-Mode
Input Bias
[3:2]
CDS Amplifier
Bias
[1:0]
CDS
Common-Mode
Input Bias
Register Name Power Level Control 1
Address
F Hex
Type
Read/Write
Reset Value
0101 1010 Binary
Bit
[7:6]
Bit Symbol
ADC Coarse
Bank Bias
Description
Adjusts the power level of
the ADC coarse bank. The
power level is relative to the
value of the binary number
stored.
Adjusts the power level of
the ADC fine bank. The
power level is relative to the
value of the binary number
stored.
Adjusts the power level of
the PGA stage 3 amplifier.
The power level is relative to
the value of the binary
number stored.
Adjusts the power level of
the PGA stage 2 amplifier.
The power level is relative to
the value of the binary
number stored.
[5:4]
ADC Fine Bank
Bias
[3:2]
PGA Stage 3
Amplifier Bias
[1:0]
PGA Stage 2
Amplifier Bias
L
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