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參數(shù)資料
| 型號(hào)： | LM98501CCVBH |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | 10-Bit, 27 MSPS Camera Signal Processor |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP48 |
| 封裝： | LQFP-48 |
| 文件頁數(shù)： | 22/24頁 |
| 文件大?。?/td> | 490K |
| 代理商： | LM98501CCVBH |
Applications Information
(Continued)
ANALOG OFFSET DAC RANGE ADJUSTMENT
The analog offset DAC has an input range of
±
127 LSB (see
Register Data). This analog offset corresponds to approxi-
mately 0.4 LSB at the ADC output per DAC input code LSB
step. Therefore, the offset DAC is limited to providing offset
values less than or equal to
±
54 LSB at the ADC output. In
some applications, this range of output may not be sufficient.
It is possible to increase the range of the DAC by adjusting
the DAC reference range. The DAC reference range may be
adjusted by lowering the voltage at the DAC lower reference
pin, VREFN via use of a pull-down resistor from VREFN to
AGND. A resistor value of x.xx k
will increase the DAC
range by a factor of 1.25x, allowing offsets of
±
64 LSB to be
applied at the ADC output rather than the default maximum
and minimum offsets of
±
54 LSB, resulting in a 2 LSB DAC
step to 1 LSB ADC output step relationship. Likewise, a re-
sistor value of 750
will increase the DAC range by a factor
of 2.5x, allowing offsets of
±
127 LSB to be applied at the
ADC output, in this configuration, 1 LSB step of the DAC cor-
responds to 1 LSB step at the ADC output.
POWER SUPPLY CONSIDERATIONS
The LM98501 may draw a sufficient amount of current to
corrupt improperly bypassed power supplies. A 10 μF to
50 μF capacitor should be placed within 1 cm of the analog
power (AV+) pins of the device in parallel with a 0.1 μF ce-
ramic chip capacitor placed as close to the device as layout
permits. Leadless chip capacitors are preferred because
they have a low lead inductance. As is the case with virtually
all high-speed semiconductors, the LM98501 should be as-
sumed to have little power supply rejection; therefore, a
noise-free analog power source is required.
The analog and digital power supplies of the LM98501
should be sourced from the same supply voltage, but the
supply pins should be well isolated from one another. Isolat-
ing the supplies prevents digital noise from coupling back
into the analog supply pins. A choke (ferrite bead) is recom-
mended to be placed between the analog and digital power
supply pins as well as a ceramic chip capacitor placed as
close as possible to the analog supply pin(s) of the device.
Additionally, it is not recommended that the LM98501’s digi-
tal supply be used for any other digital circuitry on the circuit
board. All other digital devices should be powered from a
separate digital supply well isolated from both the analog
and digital supplies of the LM98501.
THE LM98501 CLOCK
Although the LM98501 is tested and its performance guaran-
teed with a 27 MHz clock, it typically will function with clock
frequencies ranging from 1 MHz to 30 MHz. Performance is
best if the clock rise and fall times are less than 5 ns and the
clock trace is terminated near the clock input pin with a se-
ries RC network consisting of a 100
resistor and a 47 pF
capacitor.
LAYOUT AND GROUNDING TECHNIQUES
The proper routing of all signals and pertinent grounding
techniques are essential to insure the best signal-to-noise
ratio and dynamic performance possible. Separate analog
and digital ground planes ease meeting the datasheet limits.
The analog ground plane should be low impedance and free
from noise of other components of the system.All bypass ca-
pacitors should be located as close to the pin as possible
and connected to the appropriate ground plane with short
traces (
<
1 cm). The analog input should be isolated from
noisy signal traces to avoid coupling of spurious signals into
the input.
Figure 18provides an example of a suitable layout, including
power supply routing, ground plane separation, and bypass
capacitor placement. All input amplifiers, filters, and refer-
ence components should be placed on or over the analog
ground plane. All digital circuitry and I/O lines should be
placed over and grounded via the digital ground plane. Digi-
tal and analog signal lines should never run parallel to each
other in close proximity with each other. These signals
should only cross when absolutely necessary and then only
at 90 angles.
DYNAMIC PERFORMANCE
The LM98501 is AC tested and its dynamic performance is
guaranteed. The clock source driving the CLK input must be
free of jitter. For best AC performance, the clock source
should be isolated from other system digital circuitry with a
clock tree buffer(s). Meeting noise specifications depends
largely upon keeping digital noise out of the analog input of
the LM98501.
COMMON APPLICATION PITFALLS
Driving the inputs (analog or digital) beyond the power
supply potential.
For proper operation, all input potentials
should not be greater than 300 mV above that of the power
supply. It is not uncommon for high speed digital circuits
(e.g. 74F and 74AC devices) to exhibit undershoot that falls
to a potential greater than 1.0V below the ground potential
and overshoot that rises to a potential greater than 1.0V
above the power supply potential. A resistor of 50
to 100
in series with the offending digital input will, in most cases,
eliminate this problem.
Attempting to drive a high capacitance digital data bus.
The more capacitance the output drivers have to charge for
each conversion output, the more instantaneous digital cur-
rent is required from the DV+ I/O and DGND I/O supply pins.
These large charging current spikes can couple into the ana-
log section and subsequently may degrade dynamic perfor-
mance of the system. Adequate bypassing and maintaining
separate analog and digital ground planes will reduce this
problem on the application system board. Buffering the digi-
tal data outputs may be necessary if the data bus being
driven by the LM98501 is heavily loaded. Dynamic perfor-
mance may also be improved by adding series resistors of
47
at each digital output.
Driving the reference pins with devices that cannot
source or sink the current required by the reference re-
sistor ladder.
As mentioned previously, any devices driving
the reference resistor ladder must source sufficient current
into the top of the ladder. Additionally, the device connected
to the bottom of the ladder must be able to sink the neces-
sary amount of current to keep the reference voltage(s)
stable. If the reference resistor ladder voltages are not stable
the converter output will not generate predictable output
codes.
L
www.national.com
22
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