參數(shù)資料
型號： LM9800CCV
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： 模擬信號調(diào)理
英文描述： 8-Bit Greyscale/24-Bit Color Linear CCD Sensor Processor
中文描述： SPECIALTY ANALOG CIRCUIT, PQCC52
封裝： PLASTIC, LCC-52
文件頁數(shù)： 4/34頁
文件大小： 619K
代理商： LM9800CCV
DC and Logic Electrical Characteristics
The following specifications apply for AGND = DGND = DGND
= 0V, V
A
= V
D
= +5.0V
DC
, V
D(I/O)
= +5.0 or +3.0V
DC
, REF
IN = +1.225V
DC
, f
MCLK
= 20MHz, R
s
= 25
.
Boldface limits apply for T
A
= T
J
= T
MIN
to T
MAX
A
= T
J
=
25C.
Symbol
Parameter
Conditions
Typical
(Note 9)
Limits
(Note 10)
Units
(Limits)
CD0–CD6, MCLK, SYNC, SDI, SCLK, CS , RD Digital Input Characteristics
V
IN(1)
Logical “1” Input Voltage
V
D(I/O)
= 5.25V
V
D(I/O)
= 3.6V
V
D(I/O)
= 4.75V
V
D(I/O)
= 2.7V
V
IN
= V
D
V
IN
= DGND
2.0
2.0
0.8
0.7
V (min)
V (min)
V (max)
V (max)
μA
μA
pF
V
IN(0)
Logical “0” Input Voltage
I
IN
Input Leakage Current
0.1
0.1
5
C
IN
DD0–DD7, EOC , CCLK, SDO Digital Output Characteristics
V
OUT(1)
Logical “1” Output Voltage
Input Capacitance
V
D(I/O)
= 4.75V, I
OUT
= 360 μA
V
D(I/O)
= 4.75V, I
OUT
= 10 μA
V
D(I/O)
= 2.7V, I
OUT
= 360 μA
V
D(I/O)
= 2.7V, I
OUT
= 10 μA
V
D(I/O)
= 5.25V, I
OUT
= 1.6 mA
V
D(I/O)
= 3.6V, I
OUT
= 1.6 mA
V
OUT
= DGND
V
OUT
= V
D
2.4
4.4
2.1
2.5
0.4
0.4
V (min)
V (min)
V (min)
V (min)
V (max)
V (max)
μA
μA
pF
V
OUT(0)
Logical “0” Output Voltage
I
OUT
TRI-STATE
Output Current
(DD0–DD7 only)
TRI-STATE Output Capacitance
φ
1,
φ
2, RS, TR Digital Output Characteristics
V
OUT(1)
Logical “1” Output Voltage
0.1
0.1
5
C
OUT
V
D
= 4.75V, I
OUT
= 360 μA
V
D
= 4.75V, I
OUT
= 10 μA
V
D
= 5.25V, I
OUT
= 1.6 mA
2.4
4.4
0.4
V (min)
V (min)
V (max)
V
OUT(0)
Power Supply Characteristics
I
A
Analog Supply Current
Logical “0” Output Voltage
Operating
Standby
Operating
Standby
Operating, V
D(I/O)
= 5.0V
Operating, V
D(I/O)
= 3.0V
Standby, V
D(I/O)
= 5.0V or 3.0V
32
20
6
4
3.5
1.6
0.5
42
mA (max)
μA
mA (max)
mA
mA (max)
mA (max)
mA
I
D
Digital Supply Current
10
I
D(I/O)
Digital I/O Supply Current
6
2
AC Electrical Characteristics, MCLK Independent
The following specifications apply for AGND = DGND = DGND
= 0V, V
= V
= V
= +5.0V
, REF IN = +1.225V
DC
,
f
MCLK
= 20MHz, t
MCLK
= 1/f
MCLK
, t
r
= t
= 5ns, R
s
= 25
, C
L
(databus loading) = 50 pF/pin.
Boldface limits apply for T
A
T
J
MIN
to T
MAX
A
= T
J
= 25C.
Symbol
Parameter
Conditions
Typical
(Note 9)
Limits
(Note 10)
20
5
40
60
10
20
0
15
Units
(Limits)
MHz (min)
MHz (max)
% (min)
% (max)
ns (min)
ns (min)
ns (min)
ns (max)
f
MCLK
Maximum MCLK Frequency
Minimum MCLK Frequency
MCLK Duty Cycle
30
70
5
14
12
7
t
A
t
CDSETUP
t
CDHOLD
t
D1H
, t
D0H
SYNC setup of MCLK
Correction Data valid to CLK Setup
Correction Data valid to CLK Hold
RD High to DD0–DD7 TRI-STATE
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