參數(shù)資料
型號(hào)： LM9800CCV
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： 模擬信號(hào)調(diào)理
英文描述： 8-Bit Greyscale/24-Bit Color Linear CCD Sensor Processor
中文描述： SPECIALTY ANALOG CIRCUIT, PQCC52
封裝： PLASTIC, LCC-52
文件頁(yè)數(shù)： 30/34頁(yè)
文件大?。?/td> 619K
代理商： LM9800CCV
Applications Information
(Continued)
the gain correction number that is sent to the CD0–CD6 cor-
rection databus to provide gain correction for pixel n when
digitizing a line with the LM9800’s PGA gain correction oper-
ating.
All the Correction Coefficients must be stored and sent to the
LM9800 through the CD0–CD6 databus for every line
scanned.
7.0 POWER SUPPLY CONSIDERATIONS
7.1 General
The LM9800 should be powered by a single +5V source (un-
less 3V-compatible digital I/O is required— see section 7.2).
The analog supplies (V
) and the digital supplies (V
and
V
) are brought out individually to allow separate by-
passing for each supply input. They should not be powered
by two or more different supplies.
In systems with separate analog and digital +5V supplies, all
the supply pins of the LM9800 should be powered by the
cleaner analog +5V supply. Each supply input should be by-
passed to its respective ground with a 0.1μF capacitor lo-
cated as close as possible to the supply input pin. A single
10μF tantalum should be placed near the V
A
supply pin to
provide low frequency bypassing.
To minimize noise, keep the LM9800 and all analog compo-
nents as far as possible from noise generators, such as
switching power supplies and high frequency digital busses.
If possible, isolate all the analog components and signals
(OS, GAIN, reference inputs and outputs, VA, AGND, I
)
on an analog ground plane, separate from the digital ground
plane. The two ground planes should be tied together at a
single point, preferably the point where the power supply en-
ters the PCB.
7.2 3V Compatible Digital I/O
If 3V digital I/O operation is desired, the V
D(I/O)
pin may be
powered by a separate 3V
±
10% or 3.3V
±
this case all the digital I/O pins (CD0–CD6, CCLK, MCLK,
DD0–DD7, EOC , RD , SYNC, CS , SCLK, SDO, and SDI)
will be 3V compatible. (The CCD clock signals (
φ
1,
φ
2, RS,
and TR) remain 5V outputs, powered by V
D
.) In this case the
V
input should be bypassed to DGND
with a parallel
combination of a 0.1μF capacitor and a 10μF tantalum ca-
pacitor.
7.3 Power Down Mode
Setting the Power Down bit to a “1” puts the device in a low
power standby mode. The CCD outputs (
φ
1,
φ
2, RS, and TR)
are pulled low and the analog sections are turned off to con-
serve power. The digital logic will continue to operate if
MCLK continues and SYNC is held high, so for minimum
power dissipation MCLK should be stopped when the
LM9800 enters the Power Down mode. Recovery from
Power Down typically takes 50μs (the time required for the
reference voltages to settle to 0.5 LSB accuracy).
8.0 TYPICAL APPLICATION
Figure 42 shows the interface between the LM9800 and a
typical even/odd output CCD, the TCD1250. The interface
for most other CCDs will be similar, the only differences be-
ing the values for the clamp capacitor and the values for the
series resistors, if needed. The clamp capacitor value is de-
termined as shown in section 4.2. The resistor values are
usually given in the CCD’s datasheet. If the datasheet’s re-
quirement is given as a particular rise/fall time, the resistor
can be chosen using the graph of
φ
1,
φ
2, RS and TR Rise
Times Through A Series Resistance vs. Load Capaci-
tance
graph in the
Typical Performance Characteristics
section. Given the required rise time and the input capaci-
tance of the input being driven, the resistor value can be es-
timated from the graph.
Table 3 shows the Configuration Register parameters rec-
ommended for use as a starting point for most even/odd
CCDs. The Mode is set to Even/Odd, RS Pulse Width is set
to its minimum value, and RS polarity is positive. The timing,
shown in Figure 43 is determined by the RS, SR, and SS
registers. The RS pulse position (RS) is set to 10, dividing
the pixel period so that the signal portion is available for the
first 5 MCLKs following a
φ
1 clock edge and the black refer-
ence portion appears during the last 2 MCLKs (following the
1 MCLK wide reset pulse). Sample Reference (SR) is set to
14, so it samples the black reference just before the next
φ
1
clock edge. Sample Signal (SS) is set to 8, so it samples the
black reference just before the next reset pulse. These val-
ues can be adjusted to account for differences in CCDs,
CCD data delays, settling time, etc., but this is often not
necessary.
DS012498-50
FIGURE 42. CCD Interface Example
DS012498-51
FIGURE 43. Typical Even/Odd Timing
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