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參數(shù)資料
| 型號： | LM80CIMT-31 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Serial Interface ACPI-Compatible Microprocessor System Hardware Monitor |
| 中文描述： | 串行接口ACPI的兼容微處理器系統(tǒng)硬件監(jiān)視器 |
| 文件頁數(shù)： | 17/29頁 |
| 文件大?。?/td> | 435K |
| 代理商： | LM80CIMT-31 |
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Functional Description
(Continued)
By default Temperature Register data is represented by a
9-bit two’s complement digital word with the LSB having a
resolution of 0.5C:
Temperature
Digital Output
Binary
0 1111 1010
0 0011 0010
0 0000 0011
0 0000 0000
1 1111 1111
1 1100 1110
1 1001 0010
Hex
0 FAh
0 32h
0 03h
0 00h
1 FFh
1 CEh
1 92h
+125C
+25C
+1.5C
+0C
0.5C
25C
55C
Temperature Register data can also be represented by a
12-bit two’s complement digital word with a LSB of 0.0625C:
Temperature
Digital Output
Binary
0111 1100 0000
0001 1001 0000
0000 0001 0000
0000 0000 0001
0000 0000 0000
1111 1111 1111
1111 1111 0000
1110 0111 0000
1100 1001 0000
Hex
7 D0h
1 90h
0 10h
0 01h
00h
F FFh
F F0h
E 70h
C 90h
+125C
+25C
+1.0C
+0.0625C
0C
0.0625C
1.0C
25C
55C
The 8 MSBs of the Temperature reading can be found at
Value RAM address 28 h. The remainder of the Temperature
reading can be found in the OS Configuration/Temperature
Resolution Register bits 7-4. In 9-bit format bit 7 is the only
valid bit.
7.2 Temperature Interrupts
There are four Value RAM WATCHDOG limits for the Tem-
perature reading that affect the INT and OS outputs of the
LM80. They are: Hot Temperature Limit, Hot Temperature
Hysteresis Limit, OS Limit, OS Hysteresis Limit. There are
three interrupt modes of operation: “One-Time Interrupt”
mode, “Default Interrupt” mode, and “Comparator Mode”.
The OS output of the LM80 can be programmed for
“One-Time Interrupt” mode and “Comparator” mode. INT can
be programmed for “Default Interrupt” mode and “One-Time”
Interrupt.
“Default Interrupt mode”
operates in the following way: Ex-
ceeding T
causes an Interrupt that will remain active in-
definitely until reset by reading Interrupt Status Register 1 or
cleared by the INT_Clear bit in the Configuration register.
Once an Interrupt event has occurred by crossing T
, then
reset, an Interrupt will occur again once the next temperature
conversion has completed. The interrupts will continue to oc-
cur in this manner until the temperature goes below T
,
at which time the Interrupt output will automatically clear.
“One-Time Interrupt” mode
operates in the following way:
Exceeding T
causes an Interrupt that will remain active in-
definitely until reset by reading Interrupt Status Register 1 or
cleared by the INT_Clear bit in the Configuration register.
Once an Interrupt event has occurred by crossing T
, then
reset, an Interrupt will not occur again until the temperature
goes below T
hot hyst
.
“Comparator” mode
operates in the following way: Ex-
ceeding T
causes the OS output to go Low (default). OS
will remain Low until the temperature goes below T
os
. Once
the temperature goes below T
os
, OS will go High.
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