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參數(shù)資料
| 型號： | LM12434CIWM |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 模擬信號調理 |
| 英文描述： | Sign Data Acquisition System with Serial I/O and Self-Calibration |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, PDSO28 |
| 封裝： | SOP-28 |
| 文件頁數(shù)： | 10/80頁 |
| 文件大?。?/td> | 1561K |
| 代理商： | LM12434CIWM |
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2.0 Electrical Specifications
(Continued)
2.3 DIGITAL SWITCHING CHARACTERISTICS
The following specifications apply to the LM12434 and LM12
à
L
ó
438 for V
A
a
e
V
D
a e
5V
à
3.3V
ó
, AGND
e
DGND
e
0V, C
L
(load capacitance) on output lines
e
80 pF unless otherwise specified.
Boldface limits apply for T
A
e
T
J
e
T
MIN
to T
MAX
,
all other limits for T
A
e
T
J
e
25
§
C. (Notes 6, 7, and 9)
2.3.1 Standard Mode Interface (MICROWIRE/PLUS
TM
, SCI and SPI/QSPI)
Symbol
Parameter
Conditions
Typical
(Note 10)
Limits
(Note 11)
Units
(Limit)
(SeeFigure Below)
t
1
SCLK (Serial Clock) Period
100
à
125
ó
ns (min)
t
2
CS Set-Up Time to First
Clock Transition
25
à
30
ó
ns (min)
t
3
DI Valid Set-Up Time to Data
Capture Transition of SCLK
0
ns (min)
t
4
DI Valid Hold Time to Data
Capture Transition of SCLK
40
ns (min)
t
5
DO Hold Time from Data Shift
Transition of SCLK
70
à
120
ó
ns (max)
t
6
CS Hold Time from Last SCLK
Transition in a Read or Write Cycle
(Excluding Burst Read Cycle)
25
ns (min)
t
7
CS Inactive to CS Active Again
3
CLK Cycle
(min)
*
t
8
SCLK Idle Time between the
End of the Command Byte
Transfer and the Start of the
Data Transfer in Read Cycles
3
CLK Cycle
(min)
*
*
CLK is the main clock input to the device, pin number 24 in PLCC package or pin number 2 in SO package.
TL/H/11879–18
10
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相關代理商/技術參數(shù) |
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| LM12438CIV | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Sign Data Acquisition System with Serial I/O and Self-Calibration |
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