參數(shù)資料
型號(hào)： LFX500B-3F900C
廠商： Lattice Semiconductor Corporation
英文描述： The ispXPGA architecture
中文描述： 在ispXPGA架構(gòu)
文件頁(yè)數(shù)： 20/89頁(yè)
文件大?。?/td> 941K
代理商： LFX500B-3F900C
Lattice Semiconductor
ispXPGA Family Data Sheet
20
Figure 21. ispXP Block Diagram
IEEE 1149.1-Compliant Boundary Scan Testability
All ispXPGA devices have boundary scan cells and are compliant with the IEEE 1149.1 standard. This allows func-
tional testing of the circuit board on which the device is mounted through a serial scan path that can access all crit-
ical logic notes. Internal boundary scan registers are linked internally, allowing test data to be shifted in and loaded
directly onto test nodes, or test node data to be captured and shifted out for veri
fi
cation. In addition, these devices
can be linked into a board-level serial scan path for more board level testing.
Security Scheme
A programmable security scheme is provided on the ispXPGA devices as a deterrent to unauthorized copying of
the array con
fi
guration patterns. Once programmed, the security scheme prevents read-back of the programmed
pattern by a device programmer, securing proprietary designs from competitors. The entire device must be erased
in order to erase the security scheme.
Density Shifting
The ispXPGA family has been designed to ensure that different density devices in the same package have the
same pin-out. Furthermore, the architecture ensures a high success rate when performing design migration from
lower density parts to higher density parts. In many cases, it is possible to shift a lower utilization design targeted
for a high-density device to a lower density device. However, the exact details of the
fi
nal resource utilization will
impact the likely success in each case.
SRAM
Memory Space
E
2
CMOS
Memory Space
sysCONFIG Peripheral Port
sysCONFIG
ISP 1149.1 TAP Port
Power-up
Refresh
Programming
in seconds
Download in
microseconds
Configuration
in milliseconds
Port
Mode
Memory Space
ISP
1532
BACKGND
相關(guān)PDF資料
PDF描述
LFX125C-3F900C The ispXPGA architecture
LFX125B-3F900I The ispXPGA architecture
LFX125B-4F900I The ispXPGA architecture
LFX200B-4F900I The ispXPGA architecture
LFX500B-4F900I The ispXPGA architecture
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LFX500B-3F900I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:ispXPGA Family
LFX500B-3FE680C 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:ispXPGA Family
LFX500B-3FE680I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:ispXPGA Family
LFX500B-3FH516C 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:ispXPGA Family
LFX500B-3FH516I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:ispXPGA Family
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