參數(shù)資料
型號(hào)： LFX125C-3F900C
廠商： Lattice Semiconductor Corporation
英文描述： The ispXPGA architecture
中文描述： 在ispXPGA架構(gòu)
文件頁數(shù)： 1/89頁
文件大小： 941K
代理商： LFX125C-3F900C
www.latticesemi.com
1
xpga_04
ispXPGA
Family
March 2003
Preliminary Data Sheet
TM
2003 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The speci
fi
cations and information herein are subject to change without notice.
■
Non-volatile, In
fi
nitely Recon
fi
gurable
Instant-on - Powers up in microseconds via
on-chip E
2
CMOS
based memory
No external con
fi
guration memory
Excellent design security, no bit stream to intercept
Recon
fi
gure SRAM based logic in milliseconds
■
High Logic Density for System-level
Integration
139K to 1.25M system gates
160 to 496 I/O
1.8V, 2.5V, and 3.3V V
CC
operation
Up to 414Kb sysMEM embedded memory
■
High Performance Programmable Function
Unit (PFU)
Four LUT-4 per PFU supports wide and narrow
functions
Dual
fl
ip-
fl
ops per LUT-4 for extensive pipelining
Dedicated logic for adders, multipliers, multiplex-
ers, and counters
■
Variable-Length Interconnect Routing
Technology
Optimum speed, power, and
fl
exibility for logic
interconnections
■
Flexible Memory Resources
Multiple sysMEM Embedded RAM Blocks
– Single port, Dual port, and FIFO operation
64-bit distributed memory in each PFU
– Single port, Double port, FIFO, and Shift
Register operation
Table 1. ispXPGA Family Selection Guide
■
Eight sysCLOCK Phase Locked Loops
(PLLs) for Clock Management
True PLL technology
10MHz to 320MHz operation
Clock multiplication and division
Phase adjustment
Shift clocks in 250ps steps
■
sysIO for High System Performance
High speed memory support through SSTL and
HSTL
Advanced buses supported through PCI, GTL+,
LVDS, BLVDS, and LVPECL
Standard logic supported through LVTTL,
LVCMOS 3.3, 2.5, and 1.8
Programmable drive strength for series termination
Programmable bus maintenance
■
sysHSI Capability for Ultra Fast Serial
Communications
Up to 850Mbps performance
Up to 20 channels per device
Built in Clock Data Recovery (CDR) and
Serialization and De-serialization (SERDES)
■
Flexible Programming, Recon
fi
guration,
and Testing
IEEE 1532 and 1149.1 compliant
Microprocessor con
fi
guration interface
Program E
CMOS while operating from SRAM
2
ispXPGA 125
ispXPGA 200
ispXPGA 500
ispXPGA 1200
System Gates
139K
210K
476K
1.25M
PFUs
484
676
1764
3844
LUT-4s
1936
2704
7056
15376
Logic FFs
3.8K
5.4K
14.1K
30.7K
sysMEM Memory
92K
111K
184K
414K
Distributed Memory
30K
43K
112K
246K
EBR
20
24
40
90
sysHSI Channels
4
8
12
20
User I/O
160/176
160/208
336
496
Packaging
256 fpBGA
516 fpBGA
1
256 fpBGA
516 fpBGA
1
516 fpBGA
1
900 fpBGA
680 fpSBGA
900 fpBGA
1
1. Thermally enhanced package.
Note: LFX1200B/C is preliminary, LFX125/200/500B/C information is advanced.
相關(guān)PDF資料
PDF描述
LFX125B-3F900I The ispXPGA architecture
LFX125B-4F900I The ispXPGA architecture
LFX200B-4F900I The ispXPGA architecture
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