- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄377640 > LFX500B-3F900C (Lattice Semiconductor Corporation) The ispXPGA architecture PDF資料下載
參數(shù)資料
| 型號(hào)： | LFX500B-3F900C |
| 廠商： | Lattice Semiconductor Corporation |
| 英文描述： | The ispXPGA architecture |
| 中文描述： | 在ispXPGA架構(gòu) |
| 文件頁(yè)數(shù)： | 13/89頁(yè) |
| 文件大?。?/td> | 941K |
| 代理商： | LFX500B-3F900C |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)當(dāng)前第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)
Lattice Semiconductor
ispXPGA Family Data Sheet
13
Figure 13. EBR Synchronous Read Timing Diagram
Synchronous Write:
write operation begins. Once the address and data are present and the Output Enable (OE) is active, a rising clock
edge (or falling edge depending on polarity) causes the data to be stored into the EBR. Figure 14 illustrates the
synchronous write timing.
The WE signal controls the synchronous write operation. When the WE signal is high and the
Figure 14. EBR Synchronous Write Timing Diagram
Asynchronous Read:
read operation begins. Shortly after the address is present, the stored data is available on the DATA port. Figure 15
illustrates the asynchronous read timing. For more information about the EBR, refer to Lattice technical note num-
ber TN1028
ispXPGA Memory Usage Guidelines,
available at www.latticesemi.com.
The WE signal controls the asynchronous read operation. When the WE signal is low, the
Figure 15. EBR Asynchronous Read Timing Diagram
WE
CLK
CE
DATA
ADDR
OE
Valid Data
Invalid Data
Valid Data
t
EBWEEN
t
EBADDS
t
EBCO
t
EBWES
t
EBCES
t
EBCPW
t
EBOEDIS
t
EBOEEN
t
EBCEH
t
EBWEH
t
EBWEDIS
t
EBADDH
WE
CLK
WRITE
DATA
ADDR
WRITE
t
EBWEH
t
EBADDS
t
EBADDH
t
EBDATAS
t
EBDATAH
t
EBPW
t
EBWES
WE
DATA
ADDR
OE
DATA1
Invalid Data
DATA1
ADDR0
ADDR1
ADDR2
DATA0
t
EBWEEN
t
EBARADO
t
EBOEDIS
t
EBOEEN
t
EBWEDIS
t
EBARAD_H
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LFX125C-3F900C | The ispXPGA architecture |
| LFX125B-3F900I | The ispXPGA architecture |
| LFX125B-4F900I | The ispXPGA architecture |
| LFX200B-4F900I | The ispXPGA architecture |
| LFX500B-4F900I | The ispXPGA architecture |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LFX500B-3F900I | 制造商:LATTICE 制造商全稱(chēng):Lattice Semiconductor 功能描述:ispXPGA Family |
| LFX500B-3FE680C | 制造商:LATTICE 制造商全稱(chēng):Lattice Semiconductor 功能描述:ispXPGA Family |
| LFX500B-3FE680I | 制造商:LATTICE 制造商全稱(chēng):Lattice Semiconductor 功能描述:ispXPGA Family |
| LFX500B-3FH516C | 制造商:LATTICE 制造商全稱(chēng):Lattice Semiconductor 功能描述:ispXPGA Family |
| LFX500B-3FH516I | 制造商:LATTICE 制造商全稱(chēng):Lattice Semiconductor 功能描述:ispXPGA Family |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。