參數(shù)資料
型號(hào): LFEC6E-5F484C
廠商: LATTICE SEMICONDUCTOR CORP
元件分類: FPGA
英文描述: 30V N-Channel PowerTrench MOSFET
中文描述: FPGA, 768 CLBS, 6100 GATES, 420 MHz, PBGA484
封裝: 23 X 23 MM, FPBGA-484
文件頁數(shù): 65/117頁
文件大小: 557K
代理商: LFEC6E-5F484C
4-3
Pinout Information
Lattice Semiconductor
LatticeECP/EC Family Data Sheet
PICs and DDR Data (DQ) Pins Associated with the DDR Strobe (DQS) Pin
PICs Associated
with DQS Strobe
PIO Within PIC
A
B
A
B
A
B
A
B
A
B
A
B
A
B
A
B
DDR Strobe (DQS) and
Data (DQ) Pins
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
[Edge]DQSn
DQ
DQ
DQ
DQ
DQ
DQ
DQ
P[Edge] [n-4]
P[Edge] [n-3]
P[Edge] [n-2]
P[Edge] [n-1]
P[Edge] [n]
P[Edge] [n+1]
P[Edge] [n+2]
P[Edge] [n+3]
Notes:
1. “n” is a Row/Column PIC number
2. The DDR interface is designed for memories that support one DQS strobe per eight bits of
data. In some packages, all the potential DDR data (DQ) pins may not be available.
3. PIC numbering de
fi
nitions are provided in the “Signal Names” column of the Signal Descrip-
tions table.
相關(guān)PDF資料
PDF描述
LFEC6E-5F484I Octal D-type Edge-Triggered Flip-Flops With 3-State Outputs 20-TVSOP -40 to 85
LFEC6E-5F900I Octal D-type Edge-Triggered Flip-Flops With 3-State Outputs 20-TVSOP -40 to 85
LFEC6E-5T100C Octal D-type Edge-Triggered Flip-Flops With 3-State Outputs 20-TVSOP -40 to 85
LFEC6E-5T100I Octal D-type Edge-Triggered Flip-Flops With 3-State Outputs 20-SOIC -40 to 85
LFECP33E-4F256I 12-Bit, 400 kSPS ADC, Serial Out, TMS320 Compatible (up to 10MHz), Single Ch. Pseudo-differential 8-SOIC -40 to 85
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LFEC6E-5F484I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet
LFEC6E-5F672C 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet
LFEC6E-5F672I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet
LFEC6E-5F900C 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet
LFEC6E-5F900I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet