參數(shù)資料
型號(hào)： LFEC6E-5F484C
廠商： LATTICE SEMICONDUCTOR CORP
元件分類： FPGA
英文描述： 30V N-Channel PowerTrench MOSFET
中文描述： FPGA, 768 CLBS, 6100 GATES, 420 MHz, PBGA484
封裝： 23 X 23 MM, FPBGA-484
文件頁數(shù)： 32/117頁
文件大?。?/td> 557K
代理商： LFEC6E-5F484C
2-29
Architecture
Lattice Semiconductor
LatticeECP/EC Family Data Sheet
Figure 2-33. LatticeECP/EC Banks
LatticeECP/EC devices contain two types of sysIO buffer pairs.
1.
Top and Bottom sysIO Buffer Pair (Single-Ended Outputs Only)
The sysIO buffer pairs in the top and bottom banks of the device consist of two single-ended output drivers and
two sets of single-ended input buffers (both ratioed and referenced). The referenced input buffer can also be
con
fi
gured as a differential input.
The two pads in the pair are described as “true” and “comp”, where the true pad is associated with the positive
side of the differential input buffer and the comp (complementary) pad is associated with the negative side of
the differential input buffer.
Only the I/Os on the top and bottom banks have PCI clamp.
2.
Left and Right sysIO Buffer Pair (Differential and Single-Ended Outputs)
The sysIO buffer pairs in the left and right banks of the device consist of two single-ended output drivers, two
sets of single-ended input buffers (both ratioed and referenced) and one differential output driver. The refer-
enced input buffer can also be con
fi
gured as a differential input. In these banks the two pads in the pair are
described as “true” and “comp”, where the true pad is associated with the positive side of the differential I/O,
and the comp (complementary) pad is associated with the negative side of the differential I/O.
Only the left and right banks have LVDS differential output drivers.
Supported Standards
The LatticeECP/EC sysIO buffer supports both single-ended and differential standards. Single-ended standards
can be further subdivided into LVCMOS, LVTTL and other standards. The buffers support the LVTTL, LVCMOS 1.2,
1.5, 1.8, 2.5 and 3.3V standards. In the LVCMOS and LVTTL modes, the buffer has individually con
fi
gurable
V
REF1(2)
V
REF2(2)
GND
B
V
CCIO2
V
REF1(3)
V
REF2(3)
GND
B
V
CCIO3
V
REF1(7)
V
REF2(7)
GND
B
V
CCIO7
V
REF1(6)
V
REF2(6)
GND
Note: N and M are the maximum number of I/Os per bank.
B
V
CCIO6
V
R
G
Bank 5
V
C
V
R
V
R
G
Bank 4
V
C
V
R
V
R
G
Bank 0
V
C
V
R
V
R
G
Bank 1
V
C
V
R
M
相關(guān)PDF資料
PDF描述
LFEC6E-5F484I Octal D-type Edge-Triggered Flip-Flops With 3-State Outputs 20-TVSOP -40 to 85
LFEC6E-5F900I Octal D-type Edge-Triggered Flip-Flops With 3-State Outputs 20-TVSOP -40 to 85
LFEC6E-5T100C Octal D-type Edge-Triggered Flip-Flops With 3-State Outputs 20-TVSOP -40 to 85
LFEC6E-5T100I Octal D-type Edge-Triggered Flip-Flops With 3-State Outputs 20-SOIC -40 to 85
LFECP33E-4F256I 12-Bit, 400 kSPS ADC, Serial Out, TMS320 Compatible (up to 10MHz), Single Ch. Pseudo-differential 8-SOIC -40 to 85
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LFEC6E-5F484I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet
LFEC6E-5F672C 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet
LFEC6E-5F672I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet
LFEC6E-5F900C 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet
LFEC6E-5F900I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet
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