參數(shù)資料
型號： LF3370QC12
廠商： LOGIC DEVICES INC
元件分類： 消費(fèi)家電
英文描述： High-Definition Video Format Converter
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP160
封裝： PLASTIC, QFP-160
文件頁數(shù)： 14/24頁
文件大?。?/td> 412K
代理商： LF3370QC12
LF3370
High-Definition Video Format Converter
14
03/13/2001–LDS.3370-F
Video Imaging Products
DEVICES INCORPORATED
expect four values after the address value.
When loading gamma look-up tables, the
interface will expect 1024 values after the
address value. When loading HBLANK
flag counts, the interface will expect 2
values after the address value.
The coefficient banks, configuration
registers, RSL registers, etc., are not loaded
with data until all data values for the
specified address are loaded into the LF
Interface. In other words, the coefficient
banks are not written until all ten coeffi-
cients have been loaded into the LF
Interface. A RSL register is not written to
until all four data words are loaded. After
the last data value is loaded, the interface
will expect a new address value on the
next clock cycle. After the next address
value is loaded, data loading will begin
again as previously discussed.
PAUSE allows the user to effectively slow
the rate of data loading through the
LF Interface.
When PAUSE is HIGH,
the LF Interface
is held until PAUSE is
returned LOW. Figure 19 shows the
effects of PAUSE while loading Matrix
Multiplier/Key Scaler coefficients.
Table 28 shows an example of loading a
bias value into the Input Bias Adder
Register. In this example, a bias value of
007FH is loaded into the Channel ‘C’
Input Bias Adder Register 1 (0B01H).
Table 29 shows an example of loading a
bias value into the Output Bias Adder
Register. In this example, a bias value of
0010H is loaded into Channel ‘A’ Output
Bias Adder Register 3 (0903H).
Table 30 shows an example of loading
data into the Matrix Multiplier/Key
Scaler Coefficient Banks. In this example,
the following values are loaded into
Coefficient Register Set 2 (0002H): 0000H,
0001H, 0002H, 0003H, 0004H, 0005H,
0006H, 0007H, 0008H, and 0009H.
Table 31 shows an example of loading the
HF
0
Flag Count Value. In this example, a
20-bit HF
0
Flag Count Value of B3C27H is
loaded into the HF
0
Flag Count Value
BITS
FUNCTION
DESCRIPTION
1-0
Look-Up Table Control
Channel ‘A’
00 : Disable Look-Up Table
01 : Enable Look-Up Table on Input
10 : Enable Look-Up Table on Output
11 : Reserved
00 : Disable Look-Up Table
01 : Enable Look-Up Table on Input
10 : Enable Look-Up Table on Output
11 : Reserved
00 : Disable Look-Up Table
01 : Enable Look-Up Table on Input
10 : Enable Look-Up Table on Output
11 : Reserved
0 : Disable Horizontal Blanking Option
During HBLANK Period
1 : Enable Horizontal Blanking Option
During HBLANK Period
00 : Output Channel ‘A’ to W
12-0
01 : Output Channel ‘B’ to W
12-0
10 : Output Channel ‘C’ to W
12-0
11 : Output Channel ‘D’ to W
12-0
00 : Select Address Data [9:0]
01 : Select Address Data [10:1]
10 : Select Address Data [11:2]
11 : Select Address Data [12:3]
0 : Enable Input Bias
1 : Disable Input Bias
0 : Enable Output Bias
1 : Disable Output Bias
3-2
Look-Up Table Control
Channel ‘B’
5-4
Look-Up Table Control
Channel ‘C’
6
HBLANK Control
‘Key’ Channel
8-7
Data Bypass Mode ‘W’
Output Channel Mux Control
10-9
Look-Up Table Input
Address Selection Control
11
Input Bias Disable
12
Output Bias Disable
T
ABLE
6.
C
ONFIGURATION
R
EGISTER
1 – A
DDRESS
201H
BITS
FUNCTION
DESCRIPTION
1-0
Video Input Format
00 : Reserved
01 : Single Channel Interleaved Video
10 : Dual Channel Interleaved Video
11 : 3 Channel Non-Interleaved Video
00 : Reserved
01 : Single Channel Interleaved Video
10 : Dual Channel Interleaved Video
11 : 3 Channel Non-Interleaved Video
0 : Filter Feeds Matrix Multiplier
1 : Matrix Multiplier Feeds Filter
00 : Pass Through Filter
01 : Interpolate
10 : Decimate
11 : Bypass Filter
00 : Pass Through Filter
01 : Interpolate
10 : Decimate
11 : Bypass Filter
0 : Normal Order of Operations
1 : Select First Operation Only
Must be Set to Zero
3-2
Video Output Format
4
Functional Arrangement
6-5
Half-Band Filter Control
Channel ‘B’
8-7
Half-Band Filter Control
Channel ‘C’
9
First Operation Select
12-10
Reserved
T
ABLE
5.
C
ONFIGURATION
R
EGISTER
0 – A
DDRESS
200H
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