參數(shù)資料
型號： LF3370QC12
廠商： LOGIC DEVICES INC
元件分類： 消費(fèi)家電
英文描述： High-Definition Video Format Converter
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP160
封裝： PLASTIC, QFP-160
文件頁數(shù)： 10/24頁
文件大小： 412K
代理商： LF3370QC12
LF3370
High-Definition Video Format Converter
10
03/13/2001–LDS.3370-F
Video Imaging Products
DEVICES INCORPORATED
reset. HF
0
and HF
1
count value register
loading is discussed in the LF Interface.
Please note, using HBLANK is the
recommended way of clearing HF
0
and
HF
1
flags but they can be cleared by
RESET, normally performed during device
initialization. RESET will not reset the
counter.
Input/Output Bias Adder
The programmable Input/Output Bias
Adders can be used to subtract or add a
13-bit offset to the data. Input and output
data formats for the two sections are
shown in Figure 3. By using INBIAS
1-0
,
the user may select one of four pro-
grammed Input Bias Adder values (see
Figure 8). By using OUTBIAS
1-0
, the user
may select one of four programmed
Output Bias Adder values (see Figure 9).
A value of 00 on INBIAS
1-0
/OUTBIAS
1-0
selects Input/Output Bias Adder Register
0. A value of 01 selects Input/Output
Bias Adder Register 1 and so on.
INBIAS
1-0
/OUTBIAS
1-0
may be changed
every clock cycle if desired. If a bias is not
desired, then bits 11 & 12 of Configuration
Register 1 can be set up to independently
disable the input and output bias values.
Thus, effectively zeroing the function.
The total pipeline latency from the input
to the output for each of the two sections
is one CLK cycle. Input/Output Bias
Adder Register loading is discussed in the
LF Interface section.
3 x 3 Matrix Multiplier
Processing almost 550 million colors, three
simultaneous 13-bit input and output
channels are utilized to implement a 3 x 3-
matrix multiplication (triple dot product).
Each truncated 20-bit output is the sum of
all three input words multiplied by the
appropriate coefficients (see Figure 11).
These outputs are then fed into the RSL
circuitry (see Figure 13). Input/Output
formats are shown in Figure 3.
For each of the nine multipliers, up to four
user-defined 13-bit coefficients can be
programmed and selected by CA
1-0
. A
value of 00 on CA
1-0
selects Coefficient Set
0 on each of the 9 coefficient banks. A
value of 01 selects Coefficient Set 1 and so
on. CA
1-0
may be changed every clock
cycle if desired. Coefficient bank loading is
discussed in the LF Interface.
The total pipeline latency from the input of
the Matrix Multiplier to the output of the
RSL Circuitry is 6 CLK cycles and new
output data is subsequently available
every clock cycle thereafter.
If matrix multiplication is not desired,
using the appropriate combination of
coefficient values while keeping in mind
bit weighting, an identity matrix may be
set up to bypass the Matrix Multiplier
section (see also First Operation Select in
the Bypass Options discussion).
Key Scaler
The Key channel is equiped with a 13 x 13-
bit Key Scaler (see Figure 11) producing a
truncated 20-bit output which is then fed
into the RSL circuitry (see Figure 13). Up to
four user-defined 13-bit coefficients can be
programmed and selected by CA
1-0
.
Input/Output formats are shown in
Figure 3.
The total pipeline latency from the input of
the Key Scaler to the output of the RSL
Circuitry is 6 CLK cycles and new output
data is subsequently available every clock
cycle thereafter. If scaling is not desired,
load and select a Key Scaler Coefficient
value of 1
(see also First Operation Select in
the Bypass Options duscussion).
Half-Band Filter
There are two internal Half-Band filters in
the LF3370. These Half-Band filters can
either interpolate, decimate, or pass
through data found on channel B and
channel C. Data on channel A and
channel D in this section pass through a
programmable 127 x 13-bit delay (see
Bypass Section). The filter section (as
show in Figure 12) is a fixed-coefficient,
linear-phase half-band (low-pass)
interpolating/decimating digital filter.
The filter in this section is a 55-tap
transversal FIR with 13-bit coefficients as
shown in Table 3. The frequency re-
sponse (Figure 14) is in full compliance
with SMPTE 260M. This section can be
configured for 2:1 interpolation, 1:2
decimation, or pass-through mode by
setting bits 5-8 in Configuration Register 0
(see Table 5). This section can also be
placed before or after the matrix multi-
F
IGURE
12. 1:2 I
NTERPOLATION
/ 2:1 D
ECIMATION
H
ALF
-B
AND
F
ILTERS
13
B'
B
VARIABLE LENGTH BYPASS DELAY
127 x 13-Bit
INTERPOLATION
CIRCUIT
55-TAP
FIR
FILTER
13
L
R S
55-TAP
FIR
FILTER
13
L
R S
CONFIGURATION / CONTROL
REGISTERS
DECIMATION
CIRCUIT
INTERPOLATION
CIRCUIT
DECIMATION
CIRCUIT
VARIABLE LENGTH BYPASS DELAY
127 x 13-Bit
C
13
C'
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LF33AB 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Very low drop voltage regulators with inhibit
LF33ABDT 功能描述:低壓差穩(wěn)壓器 - LDO 3.3V 0.5A Positive RoHS:否 制造商:Texas Instruments 最大輸入電壓:36 V 輸出電壓:1.4 V to 20.5 V 回動電壓（最大值）:307 mV 輸出電流:1 A 負(fù)載調(diào)節(jié):0.3 % 輸出端數(shù)量: 輸出類型:Fixed 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-20
LF33ABDT-TR 功能描述:低壓差穩(wěn)壓器 - LDO 3.3V 0.5A Positive RoHS:否 制造商:Texas Instruments 最大輸入電壓:36 V 輸出電壓:1.4 V to 20.5 V 回動電壓（最大值）:307 mV 輸出電流:1 A 負(fù)載調(diào)節(jié):0.3 % 輸出端數(shù)量: 輸出類型:Fixed 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-20
LF33ABP 功能描述:低壓差穩(wěn)壓器 - LDO 3.3V 0.5A Positive RoHS:否 制造商:Texas Instruments 最大輸入電壓:36 V 輸出電壓:1.4 V to 20.5 V 回動電壓（最大值）:307 mV 輸出電流:1 A 負(fù)載調(diào)節(jié):0.3 % 輸出端數(shù)量: 輸出類型:Fixed 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-20
LF33ABPT 功能描述:低壓差穩(wěn)壓器 - LDO 3.3V 0.5A Positive RoHS:否 制造商:Texas Instruments 最大輸入電壓:36 V 輸出電壓:1.4 V to 20.5 V 回動電壓（最大值）:307 mV 輸出電流:1 A 負(fù)載調(diào)節(jié):0.3 % 輸出端數(shù)量: 輸出類型:Fixed 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-20
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