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參數(shù)資料
| 型號(hào)： | LE28DW3215AT-80 |
| 元件分類： | EEPROM |
| 英文描述： | EEPROM |
| 中文描述： | EEPROM的 |
| 文件頁(yè)數(shù)： | 3/17頁(yè) |
| 文件大?。?/td> | 125K |
| 代理商： | LE28DW3215AT-80 |
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32 Megabit FlashBank Memory
LE28DW3215AT-80
3
SANYO Electric Co., Ltd. Semiconductor Company 1-1-1 Sakata Oizumi Gunma Japan
R.0.00 (2002/2/6) No.XXXX -3/17
Write Operation Status Detection
The LE28DW3215AT-80 provides two software means to
detect the completion of a Flash bank Program cycle, in order
to optimize the system Write cycle time. The software
detection includes two status bits: Data# Polling (DQ7) and
Toggle Bit (DQ6). The end of Write Detection mode is
enabled after the rising edge of WE#, which initiates the
Internal Erase or Program cycle.
The actual completion of the nonvolatile write is a
synchronous with the system; therefore, either a Data#
Polling or Toggle Bit read may be simultaneous with the
completion of the Write cycle. If this occurs, the system will
possibly get an erroneous result, i.e. valid data may appear
to conflict with either DQ7 or DQ6. In order to prevent
spurious device rejection, if an erroneous result occurs, the
software routine should include a loop to read the accessed
location an additional two (2) times. If both reads are valid,
then the device has completed the Write cycle, otherwise the
rejection is valid.
There is no provision to abort an Erase or Program operation,
once initiated. For the SANYO Flash technology, the
associated Erase and Program times are so fast, relative to
system reset times, there is no value in aborting the
operation. Note, reads can always occur from any bank not
performing an Erase or Program operation.
Should the system reset, while a Block or Sector Erase or
Word Program is in progress in the bank where the boot
code is stored, the system must wait for the completion of the
operation before reading the bank. Since the maximum time
the system would have to wait is 25ms(for a Block Erase), the
system ability to read the boot code would not be affected.
Data# Polling (DQ7)
When the LE28DW3215AT-80 is in the internal Flash bank
Program cycle, any attempt to read DQ7 of the last word
loaded during the Flash bank Word Load cycle will receive
the complement of the true data. Once the Write cycle is
completed, DQ7 will show true data. The device is then ready
for the next operation. (See Figure 6 for the Flash bank Data
Polling timing waveforms and Figure16 for a flowchart.)
Toggle Bit (DQ6)
During the Flash bank internal Write cycle, any consecutive
attempts to read DQ6 will produce alternating 0’s and 1’s, i. e.
toggling between 0 and 1. When the Write cycle is completed,
the toggling will stop. The device is then ready for the next
operation. (See Figure 7 for the Flash bank Toggle Bit timing
waveforms and Figure16 for a flowchart.)
Hardware Data Protection
Noise/Glitch Protection: A WE# pulse of less than 5ns will not
initiate a Write cycle.
VDD Power Up/Down Detection: The Write operation is
inhibited when VDD is less than 1.5voits
Write Inhibit Mode: Forcing OE# low, CE# high, or WE# high
will inhibit the Write operation. This prevents inadvertent
writes during power-up or power-down.
The LE28DW3215AT-80 provides a protect area by hardware
protection. The assigned address is the all area of Bank1,
which is set up by WP# when low.
When this operation is executed, the functions which are
Sector erase, Block erase or Word program can not be
accepted.
When the Bank erase operation is executed, all area will be
erased except protected area.
Software Data Protection (SDP)
The LE28DW3215AT-80 provides the JEDEC approved
software data protection scheme as a requirement for
initiating a Write, Erase, or Program operation. With this
scheme, any Write operation requires the inclusion of a
series of three word-load operations to precede the Word
Program operation. The three-word load sequence is used to
initiate the Program cycle, providing optimal protection from
inadvertent Write operations, e. g., during the system power-
up or power-down. The six-word sequence is required to
initiate any Bank, Block, or Sector Erase operation.
The requirements for JEDEC compliant SDP are in byte
format. The LE28DW8163T is organized by word; therefore,
the contents of DQ8 to DQ15 are ” Don’t Care ” during any
SDP (3-word or 6-word) command sequence.
During the SDP load command sequence, the SDP load
cycle is suspended when WE# is high. This means a read
may occur to any other bank during the SDP load sequence.
The bank reserve in SDP load sequence is reserved by the
bus cycle of command materialization. If the command
sequence is aborted, e. g., an incorrect address is loaded, or
incorrect data is loaded, the device will return to the Read
mode within T
RC
of execution of the load error.
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