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| 型號： | LE28DW3215AT-80 |
| 元件分類： | EEPROM |
| 英文描述： | EEPROM |
| 中文描述： | EEPROM的 |
| 文件頁數(shù)： | 1/17頁 |
| 文件大?。?/td> | 125K |
| 代理商： | LE28DW3215AT-80 |
32 Megabit FlashBank Memory
LE28DW3215AT-80
1
SANYO Electric Co.,Ltd.Semiconductor Company 1-1-1 Sakata Oizumi Gunma Japan
The Flash Bank product family was jointly developed by SANYO and sillicon storage Technology, Inc. (SST), under SST’s technology license. This preliminary secification is subject to change without noticc.
R.0.00 (2002/2/6) No.XXXX -1/17
FEATURES:
Single 3.0-Volt Read and Write Operations
Separate Memory Banks by Address Space
Bank1: 16Mbit(1024K x 16) Flash
Bank2: 16Mbit(1024K x 16) Flash
Simultaneous Read and Write Capability
Superior Reliability
Endurance: 10,000Cycles
100,000Cycies(Erase Verify Mode)
Data Retention: 10years
Low Power Consumption
Active Current, Read:
Active Current, Read & Write: 30mA(typical)
Standby Current:
Auto Low Power Mode Current: 5uA(typical)
Fast Write Operation
Bank Erase + Program:
Block Erase + Program:
Sector Erase + Program:
10mA(typical)
5uA(typical)
15sec(typical)
500ms(typical)
45ms(typical)
Read Access Time
80nsec
Latched Address and Data
End of Write Detection
Toggle Bit / Data# Polling
Flash Bank:
Two Small Erase Element Sizes
2K Words per Sector or 32K Words per Block
Erase either element before Word Program
CMOS I/O Compatibility
Packages Available
48-Pin TSOP (10mm x 14mm)
Continuous Hardware and Software Data
Protection (SDP)
Product Description
The LE28DW3215AT-80 consists of two memory banks,
2each contains of 1024Kx16bits sector mode flash EEPROM
manufactured With SANYO’s proprietary, high performance
Flash Technology. The LE28DW3215AT-80 writes with a 3.0-
volt-only power supply.
The LE28DW3215AT-80 is divided into two separate memory
banks. Each Flash Bank is typically used for program storage
and contains 512sectors of 2K words or 32blocks of 32K
words.
Any bank may be used for executing code while writing data
to a different bank. Each memory bank is controlled by
separate Bank selection address (A20) lines.
LE28DW3215AT-80 inherently uses less energy during
Erase, and Program than alternative flash technologies. The
total energy consumed is a function of the applied voltage,
current, and time of application. Since for any given voltage
range, the Flash technology uses less current to program and
has a shorter Erase time, the total energy consumed during
any Erase or Program operation is less than alternative flash
technologies. The Auto Low Power mode automatically
reduces the active read current to approximately the same as
standby; thus, providing an average read current of
approximately 1mA/MHz of Read cycle time.
Device Operation
The LE28DW3215AT-80 operates as two independent
16Megabit Word Program, Sector Erase flash EEPROMs.
Two memory Banks are spareted by the address space.
The Bank1 is assigned as 000000h to 0FFFFFh, Bank2 is
assigned as 100000h to 1FFFFFh.
All memory banks share common I/O lines, WE#, and OE#.
Memory bank selection is by bank select address (A20).
WE# is used with SDP to control the Erase and Program
operation in each memory bank.
The LE28DW3215AT-80 provides the added functionality of
being able to simultaneously read from one memory bank
while erasing, or programming to one other memory bank.
Once the internally controlled Erase or Program cycle in a
memory bank has commenced, a different memory bank can
be accessed for read. Also, once WE# and CE# are high
during the SDP load sequence, a different bank may be
accessed to read. LE28DW3215AT-80 which selectes banks
(A20) by a address. It can be used as a normal conventinal
flash memory when operats erase or program operation to
only a bank at non-concurrent operation.
The device ID cannot be accessed while any bank is writing,
erasing, or programming.
The Auto Low Power Mode
automatically puts the
LE28DW3215AT-80 in a near standby mode after data has
been accessed with a valid Read operation. This reduces the
I
DD
active read current from typically 10mA to typically 5uA.
The Auto Low Power mode reduces the typical I
DD
active
read current to the range of 1mA/MHz of Read cycle time. If a
concurrent Read while Write is being performed, the I
DD
is
reduced to typically 40mA. The device exits the Auto Low
Power mode with any address transition or control signal
transition used to initiate another Read cycle, with no access
time penalty.
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