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參數(shù)資料
| 型號： | LC5511D |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | POWER FACTOR CONTROLLER, 18 kHz SWITCHING FREQ-MAX, DIP7 |
| 封裝： | DIP-8/7 |
| 文件頁數(shù)： | 15/40頁 |
| 文件大?。?/td> | 888K |
| 代理商： | LC5511D |
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22
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
28106.02
LC552xD/LC552xF series (isolated designs)
The soft-start
operation begins when the FB pin voltage reaches VFB(MIN)
= 0.9 V and lasts until the output current becomes constant. Dur-
ing that period, the output power gradually increases.
During this period, check the below items:
VCC pin voltage does not drop to the Operation Stop Voltage,
VCC(OFF)
Output current reaches the target value before the overload
protection (OLP) is activated by the FB pin voltage reaching
VFB(OLP)2 = 4.5 V
Quasi-Resonant Operation and Bottom-On
Timing
Figure 27 shows a basic circuit diagram of a flyback converter, in
which the energy of the transformer is transferred to the second-
ary side after the primary side MOSFET turns off.
The MOSFET drain node begins free oscillation based on the
transformer LP, and CV across the drain and source pins, after the
energy is completely transferred to the secondary. The quasi-
resonant operation is the VDS bottom-on operation that turns on
the MOSFET at the bottom point of VDS free oscillation. Because
of that, switching loss and switching noise are reduced. There-
fore, highly efficient and low noise converters can be realized.
Figure 28 shows an ideal VDS waveform of this mode. Turning
on the MOSFET at the bottom of VDS is done by creating certain
duration, delay time tONDLY, as figure 28 shows from the start of
VDS free oscillation. This delay time is created by exploiting the
auxiliary winding voltage, which synchronizes to the drain volt-
age VDS waveform and it is called the quasi-resonant signal.
Figure 29 shows the OCP pin peripheral circuit and the auxiliary
winding voltage. D6, R4, C7 and D7 form a delay circuit, and the
auxiliary winding flyback voltage, Erev1 , is fed through it
Figure 27. Basic flyback converter circuit
EIN
IOFF
VOUT
ID
Ef
NP
P
NS
CV
L
COUT
EIN: Input voltage
Ef: Flyback voltage
Ef
(VOUT + Vf)
=
NP
NS
(2)
NP: Turns count in the primary winding
NS: Turns count in the secondary winding
VOUT: Output voltage
Vf: Forward voltage of the secondary rectification diode
ID: Drain current of the power MOSFET
IOFF: Current running through the secondary diode during
the power MOSFET off-period
CV: Voltage resonant capacitor
LP: Primary inductance
Figure 28. Waveforms of the ideal Bottom-On mode
EIN
ONDLY
t
Bottom
Point
Ef
I OFF
OUT
I
tON
VDS
Half cycle of free oscillation, tONDLY ≈ √ LP × CV
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| LC5512B-10F256C | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 PROGRAM EXPANDED LOG RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| LC5512B-10F256I | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 PROGRAM EXPANDED LOG RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| LC5512B-10F484C | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 Use ispMACH 4000B RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| LC5512B-10F484I | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 Use ispMACH 4000B RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| LC5512B-10Q208C | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 Use ispMACH 4000B RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
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