參數(shù)資料
型號(hào): LAN91C100
廠商: SMSC Corporation
英文描述: FEAST⑩ Fast Ethernet Controller
中文描述: 宴⑩快速以太網(wǎng)控制器
文件頁數(shù): 5/101頁
文件大?。?/td> 312K
代理商: LAN91C100
5
DESCRIPTION OF PIN FUNCTIONSOF PIN FUNCTIONSPIN FUNCTIONS
PQFP/TQFP
PIN NO.
184
NAME
Write/nRea
d
SYMBOL
W/nR
BUFFER
TYPE
I
DESCRIPTION
Input. Defines the direction of synchronous
cycles. Write cycles when high, read cycles
when low.
181
nVL Bus
Access
nVLBUS
IP
Input.
synchronous bus interface is configured for
VL
Bus
accesses.
LAN91C100 is configured for EISA DMA
burst accesses. Does not affect the
asynchronous bus interface.
When
low
the
LAN91C100
Otherwise
the
105
Local Bus
Clock
LCLK
I
Input. Used to interface synchronous buses.
Maximum frequency is 50 MHz. Limited to
8.33 MHz for EISA DMA burst mode.
175
Asynchron-
ous Ready
ARDY
OD16
Open drain output. ARDY may be used
when interfacing asynchronous buses to
extend
accesses.
completion) edge is controlled by the XTAL1
clock and therefore asynchronous to the
host CPU or bus clock.
Its
rising
(access
106
nSynchron-
ous Ready
nSRDY
O16
Output. This output is used when
interfacing
synchronous
nVLBUS=0 to extend accesses. This signal
remains normally inactive, and its falling
edge indicates completion. This signal is
synchronous to the bus clock LCLK.
buses
and
109
nReady
Return
nRDYRTN
I
Input. This input is used to complete
synchronous read cycles. In EISA burst
mode it is sampled on falling LCLK edges,
and synchronous cycles are delayed until it
is sampled high.
176
187-189
Interrupt
INT0-INT3
O24
Outputs. Only one of these interrupts is
selected to be used; the other three are tri-
stated. The selection is determined by the
value
of
INT
SEL1-0
Configuration Register.
bits
in
the
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