參數(shù)資料
型號: LAN91C100
廠商: SMSC Corporation
英文描述: FEAST⑩ Fast Ethernet Controller
中文描述: 宴⑩快速以太網(wǎng)控制器
文件頁數(shù): 18/101頁
文件大?。?/td> 312K
代理商: LAN91C100
18
DATA STRUCTURES AND REGISTERS
PACKET FORMAT IN BUFFER MEMORY
The packet format in memory is similar for the
Transmit and Receive areas. The first word is
reserved for the status word, the next word is
used to specify the total number of bytes, and it
is followed by the data area. The data area
holds the packet itself.
FIGURE 4 – DATA PACKET FORMAT
TRANSMIT PACKET
Written by CSMA upon transmit
completion (see Status
Register)
Written by CPU
Written/modified by CPU
Written by CPU to control
odd/even data bytes
RECEIVE PACKET
Written by CSMA upon receive
completion (see RX Frame
Status Word)
Written by CSMA
Written by CSMA
Written by CSMA; also has
odd/even bit
STATUS WORD
BYTE COUNT
DATA AREA
CONTROL BYTE
RESERVED
BYTE COUNT
STATUS WORD
LAST DATA BYTE (if odd)
bit 0
bit 15
RAM
OFFSET
(Decimal)
0
2
4
2046 Max
CONTROL BYTE
DATA AREA
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