參數(shù)資料
型號: LAN9116
廠商: SMSC Corporation
英文描述: Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller
中文描述: 高效的單芯片10/100非PCI以太網(wǎng)控制器
文件頁數(shù): 85/126頁
文件大?。?/td> 831K
代理商: LAN9116
Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
5.3.18
SMSC LAN9116
85
Revision 1.1 (05-17-05)
DATASHEET
FREE_RUN—Free-Run 25MHz Counter
This register reflects the value of the free-running 25MHz counter.
5.3.19
RX_DROP– Receiver Dropped Frames Counter
This register indicates the number of receive frames that have been dropped.
Offset:
9Ch
Size:
32 bits
BITS
DESCRIPTION
TYPE
DEFAULT
31:0
Free Running SCLK Counter (FR_CNT):
Note:
This field reflects the value of a free-running 32-bit counter. At reset
the counter starts at zero and is incremented for every 25MHz
cycle. When the maximum count has been reached the counter will
rollover. When read in 16-bit mode the count value is latched on
the first read. The FREE_RUN counter can take up to 160nS to
clear after a reset event.
Note:
This counter will run regardless of the power management states
D0, D1 or D2.
RO
-
Offset:
A0h
Size:
32 bits
BITS
DESCRIPTION
TYPE
DEFAULT
31-0
RX Dropped Frame Counter (RX_DFC).
This counter is incremented every
time a receive frame is dropped. RX_DFC is cleared on any read of this
register.
An interrupt can be issued when this counter passes through its halfway
point (7FFFFFFFh to 80000000h).
RC
00000000h
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