參數(shù)資料
型號(hào): LAN9116
廠商: SMSC Corporation
英文描述: Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller
中文描述: 高效的單芯片10/100非PCI以太網(wǎng)控制器
文件頁數(shù): 113/126頁
文件大小: 831K
代理商: LAN9116
Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
SMSC LAN9116
113
Revision 1.1 (05-17-05)
DATASHEET
Note:
A PIO Read cycle begins when both nCS and nRD are asserted. The cycle ends when either
or both nCS and nRD are deasserted. They may be asserted and deasserted in any order.
6.3
PIO Burst Reads
In this mode, performance is improved by allowing up to 8, DWORD read cycles, or 16, WORD read
cycles back-to-back. PIO Burst Reads can be performed using Chip Select (nCS) or Read Enable
(nRD). Either or both of these control signals must go high between bursts for the period specified.
Timing for 16-bit and 32-bit PIO Burst Mode Read cycles is identical, with the exception that D[31:16]
are not driven during a 16-bit burst.
Table 6.3 PIO Read Timing
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
t
cycle
Read Cycle Time
165
ns
t
csl
nCS, nRD Assertion Time
32
ns
t
csh
nCS, nRD Deassertion Time
13
ns
t
csdv
nCS, nRD Valid to Data Valid
30
ns
t
asu
Address Setup to nCS, nRD Valid
0
ns
t
ah
Address Hold Time
0
ns
t
don
Data Buffer Turn On Time
0
ns
t
doff
Data Buffer Turn Off Time
7
ns
t
doh
Data Output Hold Time
0
ns
Figure 6.2 LAN9116 PIO Burst Read Cycle Timing
Data Bus
nCS, nRD
A[7:5]
A[4:1]
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