參數資料
型號: LAN9116
廠商: SMSC Corporation
英文描述: Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller
中文描述: 高效的單芯片10/100非PCI以太網控制器
文件頁數: 73/126頁
文件大?。?/td> 831K
代理商: LAN9116
Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
5.3.6
SMSC LAN9116
73
Revision 1.1 (05-17-05)
DATASHEET
FIFO_INT—FIFO Level Interrupts
This register configures the limits where the FIFO Controllers will generate system interrupts.
5.3.7
RX_CFG—Receive Configuration Register
This register controls the LAN9116 receive engine.
Offset:
68h
Size:
32 bits
BITS
DESCRIPTION
TYPE
DEFAULT
31-24
TX Data Available Level.
The value in this field sets the level, in number
of 64 Byte blocks, at which the TX FIFO Available interrupt (TFDA) will be
generated. When the TX data FIFO free space is greater than this value a
TX FIFO Available interrupt (TDFA) will be generated.
R/W
48h
23-16
TX Status Level.
The value in this field sets the level, in number of
DWORDs, at which the TX Status FIFO Level interrupt (TSFL) will be
generated. When the TX Status FIFO used space is greater than this value
an TX Status FIFO Level interrupt (TSFL) will be generated.
R/W
00h
15-8
RX Space Available Level.
The value in this field sets the level, in number
of 64 Byte blocks, at which the RX data FIFO Level interrupt (RDFL) will be
generated. When the RX data FIFO free space is less than this value an RX
data FIFO Level interrupt (RDFL) will be generated.
R/W
00h
7-0
RX Status Level.
The value in this field sets the level, in number of
DWORDs, at which the RX Status FIFO Level interrupt (RSFL) will be
generated. When the RX Status FIFO used space is greater than this value
an RX Status FIFO Level interrupt (RSFL) will be generated.
R/W
00h
Offset:
6Ch
Size:
32 bits
BITS
DESCRIPTION
TYPE
DEFAULT
31:30
RX End Alignment.
This field specifies the alignment that must be
maintained on the last data transfer of a buffer. The LAN9116 will add
extra DWORDs of data up to the alignment specified in the table below.
The host is responsible for removing these extra DWORDs. This
mechanism can be used to maintain cache line alignment on host
processors.
Please refer to
Table 5.2
for bit definitions
Note:
The desired RX End Alignment must be set before reading a
packet. The RX end alignment can be changed between reading
receive packets, but must not be changed if the packet is
partially read.
R/W
00b
29-28
Reserved
RO
-
27-16
RX DMA Count (RX_DMA_CNT).
This 12-bit field indicates the amount
of data, in DWORDS, to be transferred out of the RX data FIFO before
asserting the RXD_INT. After being set, this field is decremented for each
DWORD of data that is read from the RX data FIFO. This field can be
overwritten with a new value before it reaches zero.
R/W
000h
相關PDF資料
PDF描述
LAN9117 HIGH PERFORMANCE SINGLE-CHIP 10/100 NON-PCI ETHERNET CONTROLLER
LAN9117-MD HIGH PERFORMANCE SINGLE-CHIP 10/100 NON-PCI ETHERNET CONTROLLER
LAN9117-MT HIGH PERFORMANCE SINGLE-CHIP 10/100 NON-PCI ETHERNET CONTROLLER
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LAN9118-MD HIGH PERFORMANCE SINGLE CHIP 10/100NON PCI ETHERNET CONTROLLER
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LAN9116-MT 功能描述:以太網 IC Ethernet IC 32bit Superior Perf RoHS:否 制造商:Micrel 產品:Ethernet Switches 收發(fā)器數量:2 數據速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray
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LAN9117-MD 功能描述:以太網 IC HiPerfrm Sngl-Chip 10/100 Ethrnt RoHS:否 制造商:Micrel 產品:Ethernet Switches 收發(fā)器數量:2 數據速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray
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