參數(shù)資料
型號: LAN9116
廠商: SMSC Corporation
英文描述: Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller
中文描述: 高效的單芯片10/100非PCI以太網(wǎng)控制器
文件頁數(shù): 79/126頁
文件大?。?/td> 831K
代理商: LAN9116
Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
SMSC LAN9116
79
Revision 1.1 (05-17-05)
DATASHEET
5.3.12
TX_FIFO_INF—Transmit FIFO Information Register
This register contains the free space in the transmit data FIFO and the used space in the transmit
status FIFO in the LAN9116.
5.3.13
PMT_CTRL— Power Management Control Register
This register controls the Power Management features. This register can be read while the
LAN9116
is in a power saving mode.
Note:
The LAN9116 must always be read at least once after power-up, reset, or upon return from a
power-saving state or write operations will not function.
15-0
RX Data FIFO Used Space (RXDUSED).
). Reads the amount of space in
bytes, used in the RX data FIFO. For each receive frame, this field is
incremented by the length of the receive data rounded up to the nearest
DWORD (if the payload does not end on a DWORD boundary).
RO
0000h
Offset:
80h
Size:
32 bits
BITS
DESCRIPTION
TYPE
DEFAULT
31-24
Reserved
RO
-
23-16
TX Status FIFO Used Space (TXSUSED).
Indicates the amount of space
in DWORDS used in the TX Status FIFO.
RO
00h
15-0
TX Data FIFO Free Space (TDFREE).
Reads the amount of space in bytes,
available in the TX data FIFO. The application should never write more data
than is available, as indicated by this value.
RO
1200h
Offset:
84h
Size:
32 bits
BITS
DESCRIPTION
TYPE
DEFAULT
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