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參數(shù)資料
| 型號(hào)： | LAN8187_06 |
| 廠商： | SMSC Corporation |
| 英文描述： | 【15kV ESD Protected MII/RMII Fast-Ethernet PHY with HP Auto-MDIX and SMSC flexPWRTM |
| 中文描述： | 【15kV的ESD保護(hù)信息產(chǎn)業(yè)部/ RMII快速以太網(wǎng)PHY與HP Auto - MDIX功能和SMSC flexPWRTM |
| 文件頁(yè)數(shù)： | 20/72頁(yè) |
| 文件大?。?/td> | 433K |
| 代理商： | LAN8187_06 |
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±15kV ESD Protected MII/RMII Fast-Ethernet PHY with HP Auto-MDIX and SMSC flexPWR
TM
Datasheet
SMSC LAN8187/LAN8187I
20
Revision 1.0 (12-14-06)
DATASHEET
4.2.3
Scrambling
Repeated data patterns (especially the IDLE code-group) can have power spectral densities with large
narrow-band peaks. Scrambling the data helps eliminate these peaks and spread the signal power
more uniformly over the entire channel bandwidth. This uniform spectral density is required by FCC
regulations to prevent excessive EMI from being radiated by the physical wiring.
The seed for the scrambler is generated from the PHY address, PHYAD[4:0], ensuring that in multiple-
PHY applications, such as repeaters or switches, each PHY will have its own scrambler sequence.
The scrambler also performs the Parallel In Serial Out conversion (PISO) of the data.
4.2.4
NRZI and MLT3 Encoding
The scrambler block passes the 5-bit wide parallel data to the NRZI converter where it becomes a
serial 125MHz NRZI data stream. The NRZI is encoded to MLT-3. MLT3 is a tri-level code where a
change in the logic level represents a code bit “1” and the logic output remaining at the same level
represents a code bit “0”.
4.2.5
100M Transmit Driver
The MLT3 data is then passed to the analog transmitter, which drives the differential MLT-3 signal, on
outputs TXP and TXN, to the twisted pair media across a 1:1 ratio isolation transformer. The 10Base-
T and 100Base-TX signals pass through the same transformer so that common “magnetics” can be
used for both. The transmitter drives into the 100
Ω
impedance of the CAT-5 cable. Cable termination
and impedance matching require external components.
4.2.6
100M Phase Lock Loop (PLL)
The 100M PLL locks onto reference clock and generates the 125MHz clock used to drive the 125 MHz
logic and the 100Base-Tx Transmitter.
00010
V
INVALID, RX_ER if during RX_DV
INVALID
00011
V
INVALID, RX_ER if during RX_DV
INVALID
00101
V
INVALID, RX_ER if during RX_DV
INVALID
01000
V
INVALID, RX_ER if during RX_DV
INVALID
01100
V
INVALID, RX_ER if during RX_DV
INVALID
10000
V
INVALID, RX_ER if during RX_DV
INVALID
Table 4.1 4B/5B Code Table (continued)
CODE
GROUP
SYM
RECEIVER
INTERPRETATION
TRANSMITTER
INTERPRETATION
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| LAN8187-JT | 功能描述:以太網(wǎng) IC HiPerfrm Ethrnt PHY RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
| LAN83C171 | 制造商:SMSC 制造商全稱(chēng):SMSC 功能描述:EPIC/XF ACPI/PC 97 Compliant Integrated PCI 10/100 Mbps Fast Ethernet Controller |
| LAN83C171 WAF | 制造商:SMSC 功能描述: |
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