參數(shù)資料
型號: LAN8187_06
廠商: SMSC Corporation
英文描述: 【15kV ESD Protected MII/RMII Fast-Ethernet PHY with HP Auto-MDIX and SMSC flexPWRTM
中文描述: 【15kV的ESD保護信息產業(yè)部/ RMII快速以太網(wǎng)PHY與HP Auto - MDIX功能和SMSC flexPWRTM
文件頁數(shù): 13/72頁
文件大?。?/td> 433K
代理商: LAN8187_06
±15kV ESD Protected MII/RMII Fast-Ethernet PHY with HP Auto-MDIX and SMSC flexPWR
TM
Datasheet
Revision 1.0 (12-14-06)
13
SMSC LAN8187/LAN8187I
DATASHEET
RXD0
O
Receive Data 0
: Bit 0 of the 4 data bits that are sent by the PHY
in the receive path.
RXD1
O
Receive Data 1
: Bit 1 of the 4 data bits that are sent by the PHY
in the receive path.
RXD2
O
Receive Data 2
: Bit 2 of the 4 data bits that sent by the PHY in
the receive path.
Note:
This signal is not used in RMII Mode.
RXD3/
nINTSEL
O
Receive Data 3
: Bit 3 of the 4 data bits that sent by the PHY in
the receive path.
nINTSEL
: On power-up or external reset, the mode of the
nINT/TXER/TXD4 pin is selected.
When floated or pulled to VDDIO, nINT is selected (default).
When pulled low to VSS through a Pull-down resistor (see
Table 4.4, “Boot Strapping Configuration Resistors,” on
page 32
), TXER/TXD4 is selected.
Notes:
RXD3 is not used in RMII Mode
If the nINT/TXER/TXD4 pin is configured for nINT mode, it
needs a pull-up resistor to VDDIO.
See
Section 4.10, "(TX_ER/TXD4)/nINT Strapping," on
page 31
for additional information on configuration/strapping
options.
RX_ER/
RXD4
I/O
Receive Error
: Asserted to indicate that an error was detected
somewhere in the frame presently being transferred from the
PHY.
MII Receive Data 4
: In Symbol Interface (5B Decoding) mode,
this signal is the MII Receive Data 4 signal, the MSB of the
received 5-bit symbol code-group.
Notes:
The RX_ER signal is optional in RMII Mode.
RX_CLK
O
Receive Clock
: 25MHz in 100Base-TX mode. 2.5MHz in
10Base-T mode.
Notes:
This signal is not used in RMII Mode
COL/CRS_DV
O
MII Collision Detect
: Asserted to indicate detection of collision
condition.
RMII CRS_DV (Carrier Sense/Receive Data Valid)
Asserted to
indicate when the receive medium is non-idle. When a 10BT
packet is received, CRS_DV is asserted, but RXD[1:0] is held
low until the SFD byte (10101011) is received. In 10BT, half-
duplex mode, transmitted data is not looped back onto the
receive data pins, per the RMII standard.
Note:
See
Section 4.6.3, "MII vs. RMII Configuration," on
page 26
for more details.
Table 3.1 MII Signals (continued)
SIGNAL NAME
TYPE
DESCRIPTION
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