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參數(shù)資料
| 型號： | L6732 |
| 廠商： | 意法半導體 |
| 英文描述： | Adjustable step-down controller with synchronous rectification |
| 中文描述： | 可調式降壓同步整流控制器 |
| 文件頁數(shù)： | 24/33頁 |
| 文件大?。?/td> | 735K |
| 代理商： | L6732 |
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Application details
L6732
24/33
6.4
Compensation network
The loop is based on a voltage mode control (
Figure 18.
). The output voltage is regulated to the
internal/external reference voltage and scaled by the external resistor divider. The error
amplifier output V
COMP
is then compared with the oscillator triangular wave to provide a pulse-
width modulated (PWM) with an amplitude of V
IN
at the PHASE node. This waveform is filtered
by the output filter. The modulator transfer function is the small signal transfer function of V
OUT
/
V
COMP
. This function has a double pole at frequency F
LC
depending on the L-C
OUT
resonance
and a zero at FESR depending on the output capacitor's ESR. The DC Gain of the modulator is
simply the input voltage V
IN
divided by the peak-to-peak oscillator voltage: V
OSC
.
The compensation network consists in the internal error amplifier, the impedance networks Z
IN
(R3, R4 and C20) and Z
FB
(R5, C18 and C19). The compensation network has to provide a
closed loop transfer function with the highest 0dB crossing frequency to have fastest transient
response (but always lower than fsw/10) and the highest gain in DC conditions to minimize the
load regulation error. A stable control loop has a gain crossing the 0dB axis with -20dB/decade
slope and a phase margin greater than 45°. To locate poles and zeroes of the compensation
networks, the following suggestions may be used:
Modulator singularity frequencies:
●
●
Compensation network singularity frequencies:
Figure 18. Compensation Network
Cout
L
LC
=
1
ω
Cout
ESR
ESR
=
1
ω
(13)
(14)
+
=
19
18
19
18
5
1
1
C
C
C
C
R
P
ω
20
4
2
1
C
R
P
=
ω
(15)
(16)
19
5
1
1
C
R
Z
=
ω
(
)
4
3
20
2
1
R
R
C
Z
+
=
ω
(17)
(18)
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