參數(shù)資料
型號: L6732
廠商: 意法半導(dǎo)體
英文描述: Adjustable step-down controller with synchronous rectification
中文描述: 可調(diào)式降壓同步整流控制器
文件頁數(shù): 16/33頁
文件大小: 735K
代理商: L6732
Device description
L6732
16/33
5.7
Driver section
The high-side and low-side drivers allow using different types of power MOSFETs (also multiple
MOSFETs to reduce the R
DSON
), maintaining fast switching transitions. The low-side driver is
supplied by V
CCDR
while the high-side driver is supplied by the BOOT pin. A predictive dead
time control avoids MOSFETs cross-conduction maintaining very short dead time duration in
the range of 20ns. The control monitors the phase node in order to sense the low-side body
diode recirculation. If the phase node voltage is less than a certain threshold (-350mV typ.)
during the dead time, it will be reduced in the next PWM cycle. The predictive dead time control
doesn't work when the high-side body diode is conducting because the phase node doesn't go
negative. This situation happens when the converter is sinking current for example and, in this
case, an adaptive dead time control operates.
5.8
Monitoring and protections
The output voltage is monitored by means of pin FB. If it is not within ±10% (typ.) of the
programmed value, the Power-Good (PGOOD) output is forced low.
The device provides over-voltage-protection: when the voltage sensed on FB pin reaches a
value 20% (typ.) greater than the reference, the low-side driver is turned on as long as the over
voltage is detected (see
Figure 10.
).
It must be taken into account that there is an electrical network between the output terminal and
the FB pin and therefore the voltage at the pin is not a perfect replica of the output voltage.
However due to the fact that the converter can sink current, in the most of cases the low-side
will turn-on before the output voltage exceeds the over-voltage threshold, because the error
amplifier will throw off balance in advance. Even if the device doesn't report an over-voltage, the
behavior is the same, because the low-side is turned-on immediately. The following figure
shows the device behavior during an over-voltage event. The output voltage rises with a slope
of 100mV/μs, emulating in this way the breaking of the high-side MOSFET as an over-voltage
cause.
Figure 10. OVP
LGate
FB
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