參數(shù)資料
型號: L6732
廠商: 意法半導(dǎo)體
英文描述: Adjustable step-down controller with synchronous rectification
中文描述: 可調(diào)式降壓同步整流控制器
文件頁數(shù): 23/33頁
文件大?。?/td> 735K
代理商: L6732
L6732
Application details
23/33
6.2
Output capacitors
The output capacitors are basic components for the fast transient response of the power supply.
They depend on the output voltage ripple requirements, as well as any output voltage deviation
requirement during a load transient. During a load transient, the output capacitors supply the
current to the load or absorb the current stored in the inductor until the converter reacts. In fact,
even if the controller recognizes immediately the load transient and sets the duty cycle at 100%
or 0%, the current slope is limited by the inductor value. The output voltage has a first drop due
to the current variation inside the capacitor (neglecting the effect of the ESL):
Moreover, there is an additional drop due to the effective capacitor discharge or charge that is
given by the following formulas:
Formula (8) is valid in case of positive load transient while the formula (9) is valid in case of
negative load transient. D
MAX
is the maximum duty cycle value that in the L6732 is 100%. For a
given inductor value, minimum input voltage, output voltage and maximum load transient, a
maximum ESR and a minimum C
OUT
value can be set. The ESR and C
OUT
values also affect
the static output voltage ripple. In the worst case the output voltage ripple can be calculated
with the following formula:
Usually the voltage drop due to the ESR is the biggest one while the drop due to the capacitor
discharge is almost negligible.
6.3
Input capacitors
The input capacitors have to sustain the RMS current flowing through them, that is:
Where D is the duty cycle. The equation reaches its maximum value, I
OUT
/2 with D = 0.5. The
losses in worst case are:
ESR
Iout
Vout
ESR
=
)
max
min
,
(
2
2
Vout
D
Vin
Cout
L
Iout
Vout
COUT
=
Vout
Cout
L
Iout
Vout
COUT
=
2
2
)
8
1
(
Fsw
Cout
ESR
I
Vout
L
+
=
)
1
D
D
Iout
Irms
=
2
)
5
Iout
ESR
P
=
(7)
(8)
(9)
(10)
(11)
(12)
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