參數(shù)資料
型號: L6732
廠商: 意法半導體
英文描述: Adjustable step-down controller with synchronous rectification
中文描述: 可調(diào)式降壓同步整流控制器
文件頁數(shù): 11/33頁
文件大小: 735K
代理商: L6732
L6732
Device description
11/33
5
Device description
5.1
Oscillator
The switching frequency can be fixed to two values: 250KHz or 500KHz by setting the proper
voltage at the EAREF pin (see
Table 3.
Pins function and section 4.3 Internal and external
reference).
5.2
Internal LDO
An internal LDO supplies the internal circuitry of the device. The input of this stage is the V
CC
pin and the output (5V) is the V
CCDR
pin (
Figure 3.
).
The LDO can be by-passed, providing directly a 5V voltage to V
CCDR
. In this case V
CC
and
V
CCDR
pins must be shorted together as shown in
Figure 4.
V
CCDR
pin must be filtered with at
least 1μF capacitor to sustain the internal LDO during the recharge of the bootstrap capacitor.
V
CCDR
also represents a voltage reference for PGOOD pin (see
Table 3.
Pins Function).
Figure 3.
LDO block diagram.
LDO
4.5
÷
14V
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