參數(shù)資料
型號: L6710
廠商: 意法半導體
英文描述: 6 BIT PROGRAMMABLE DUAL-PHASE CONTROLLER WITH DYNAMIC VID MANAGEMENT
中文描述: 6位可編程雙相與動態(tài)VID管理控制器
文件頁數(shù): 22/34頁
文件大?。?/td> 1610K
代理商: L6710
L6710
22/34
Considering now that in the application of interest it can be assumed that Ro>>R
L
; ESR<<Ro and
R
DROOP
<<Ro, it results:
The ACM control loop gain is designed to obtain a high DC gain to minimize static error and cross the 0dB
axes with a constant -20dB/dec slope with the desired crossover frequency
ω
T
. Neglecting the effect of
Z
F
(s), the transfer function has one zero and two poles. Both the poles are fixed once the output filter is
designed and the zero is fixed by ESR and the Droop resistance. To obtain the desired shape an R
F
-C
F
series network is considered for the Z
F
(s) implementation. A zero at
ω
F
=1/R
F
C
F
is then introduced togeth-
er with an integrator. This integrator minimizes the static error while placing the zero in correspondence
with the L-C resonance a simple -20dB/dec shape of the gain is assured (See Figure 15). In fact, consid-
ering the usual value for the output filter, the LC resonance results to be at frequency lower than the above
reported zero.
Compensation network can be simply designed placing
ω
Z
=
ω
LC
and imposing the cross-over frequency
T as desired obtaining:
Figure 15. ACM Control Loop Gain Block Diagram (left) and Bode Diagram (right).
LAYOUT GUIDELINES
Since the device manages control functions and high-current drivers, layout is one of the most important
things to consider when designing such high current applications.
A good layout solution can generate a benefit in lowering power dissipation on the power paths, reducing
radiation and a proper connection between signal and power ground can optimize the performance of the
control loops.
Integrated power drivers reduce components count and interconnections between control functions and
drivers, reducing the board space.
Here below are listed the main points to focus on when starting a new layout and rules are suggested for
a correct implementation.
G
LOOP
s
( )
4
5
--
V
V
OSC
------------------
Z
s
( )
R
FB
--------------
1
s Co
R
ESR
+
(
)
+
s
2
Co
L
2
--
s
2 Ro
---------------
Co ESR
Co
L
2
------
+
+
1
+
+
----------------------------------------------------------------------------------------------------------------------------------
=
R
F
R
V
V
IN
----------------------------------
5
4
--
ω
T
2
R
DROOP
ESR
+
(
)
-------------------------------------------------------
C
F
Co
L
2
--
R
F
-------------------
=
=
Rout
Cout
ESR
L/2
R
FB
R
F
C
F
REF
PWM
I
FB
V
COMP
V
OUT
d
V
IN
Z
F
dB
ω
ω
T
ω
Z
ω
LC
G
LOOP
Z
F
(s)
K
dB
FB
OSC
IN
R
1
V
V
5
4
K
=
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