參數(shù)資料
型號(hào): L6710
廠商: 意法半導(dǎo)體
英文描述: 6 BIT PROGRAMMABLE DUAL-PHASE CONTROLLER WITH DYNAMIC VID MANAGEMENT
中文描述: 6位可編程雙相與動(dòng)態(tài)VID管理控制器
文件頁數(shù): 18/34頁
文件大?。?/td> 1610K
代理商: L6710
L6710
18/34
Figure 11. Power Down: 0A (left), resistive load (right); CH1= Vout; CH2,CH3 = LS; CH4 =V in
When shutting the system down, the device continues regulating until Vcc becomes lower than the turn-
off threshold. After that point, the device will shut down all power mosfets.
INPUT CAPACITOR
The input capacitor is designed considering mainly the input RMS current that depends on the duty cycle
as reported in figure 12. Considering the dual-phase topology, the input RMS current is highly reduced
comparing with a single-phase operation. It can be observed that the input RMS value is one half of the
single-phase equivalent input current in the worst case condition that happens for D=0.25 and D=0.75.
The power dissipated by the input capacitance is then equal to:
Input capacitor is designed in order to sustain the ripple relative to the maximum load duty cycle. To reach
the high RMS value needed by the CPU power supply application and also to minimize components cost,
the input capacitance is realized by more than one physical capacitor. The equivalent RMS current is sim-
ply the sum of the single capacitor's RMS current.
Figure 12. Input RMS Current vs. Duty Cycle (D) and Driving Relationships.
P
RMS
ESR
I
RMS
(
)
2
=
0.50
0.75
0.25
0.50
0.25
Single Phase
Dual Phase
Duty Cycle (V
OUT
/V
IN
)
R
R
/
O
)
I
rms
I
2
I
2
-----------
2D
1
2D
(
)
if D < 0.5
-----------
2D
1
(
)
2
2D
(
)
if D > 0.5
=
Where D = V
OUT
/V
IN
is the operative duty cycle for each phase
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