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參數(shù)資料
| 型號(hào)： | L6566BTR |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | 0.8 A POWER FACTOR CONTROLLER, 900 kHz SWITCHING FREQ-MAX, PDSO16 |
| 封裝： | LEAD FREE, SOP-16 |
| 文件頁數(shù)： | 35/51頁 |
| 文件大?。?/td> | 624K |
| 代理商： | L6566BTR |
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Application information
L6566B
40/51
5.13
Slope compensation
The pin MODE/SC (12), when not connected to VREF, provides a voltage ramp during
MOSFET’s ON-time synchronous to that of the internal oscillator sawtooth, with 0.8 mA
minimum current capability. This ramp is intended for implementing additive slope
compensation on current sense. This is needed to avoid the sub-harmonic oscillation that
arises in all peak-current-mode-controlled converters working at fixed frequency in
continuous conduction mode with a duty cycle close to or exceeding 50 %.
Figure 27.
Slope compensation waveforms
The compensation will be realized by connecting a programming resistor between this pin
and the current sense input (pin 7, CS). The CS pin has to be connected to the sense
resistor with another resistor to make a summing node on the pin. Since no ramp is
delivered during MOSFET OFF-time (see Figure 27), no external component other than the
programming resistor is needed to ensure a clean operation at light loads.
Note:
The addition of the slope compensation ramp will reduce the available dynamics of the
current signal; thereby, the value of the sense resistor must be determined taking this into
account. Note also that the burst-mode threshold (in terms of power) will be slightly
changed.
If slope compensation is not required with FF operation, the pin shall be left floating.
Internal
GD
(pin 4)
MODE/SC
(pin 12)
t
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