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參數(shù)資料
| 型號(hào)： | L6566BTR |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | 0.8 A POWER FACTOR CONTROLLER, 900 kHz SWITCHING FREQ-MAX, PDSO16 |
| 封裝： | LEAD FREE, SOP-16 |
| 文件頁數(shù)： | 30/51頁 |
| 文件大小： | 624K |
| 代理商： | L6566BTR |
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Application information
L6566B
36/51
Figure 23.
OVP function: timing diagram
The value of RZ1 will be such that the current sourced by the ZCD pin be within the rated
capability of the internal clamp:
Equation 14
where Vinmax is the maximum dc input voltage and Ns the turn number of the primary
for additional details.
To reduce sensitivity to noise and prevent the latch from being erroneously activated, first
the OVP comparator is active only for a small time window (typically, 0.5 s) starting 2 s
after MOSFET’s turn-off, to reject the voltage spike associated to the positive-going edges
of the voltage across the auxiliary winding Vaux; second, to stop the L6566B the OVP
comparator must be triggered for four consecutive switching cycles. A counter, which is
reset every time the OVP comparator is not triggered in one switching cycle, is provided to
this purpose.
shows the internal block diagram, while the timing diagrams in
illustrate the operation.
Note:
To use the OVP function effectively, i.e. to ensure that the OVP comparator will be always
interrogated during MOSFET’s OFF-time, the duty cycle D under open-loop conditions must
fulfill the following inequality:
t
GD
(pin 4)
Vaux
5V
t
STROBE
t
COUNTER
RESET
t
COUNTER
STATUS
t
0
ZCD
(pin 11)
2 s
0.5s
OVP
FAULT
00
0
0 →11 →22 →00 →11 →22 →33 →4
0
NORMAL OPERATION
TEMPORARY DISTURBANCE
FEEDBACK LOOP FAILURE
t
COUT
t
max
3
1
Z
Vin
Np
Naux
10
3
1
R
≥
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