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參數(shù)資料
| 型號： | L64767 |
| 廠商： | LSI CORP |
| 元件分類： | 消費家電 |
| 英文描述： | SMATV（Satellite Master Antenna Television） QAM Encoder(衛(wèi)星主天線電視正交振幅調制編碼器) |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP100 |
| 封裝： | MQUAD-100 |
| 文件頁數(shù)： | 9/32頁 |
| 文件大?。?/td> | 298K |
| 代理商： | L64767 |
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L64767 SMATV QAM Encoder
9
Global Control and Synchronization Module
The L64767’s clocking scheme uses two independent clock signals
(ICLK, OCLK) to control incoming data, internal data processing, and
decoded output data. These clocks provide the timing for two circular
FIFO buffers that read and write data. Data on the FIFO input is latched
with respect to the valid rising edges of ICLK. Data on the FIFO output
is read with respect to the valid rising edge of OCLK.
A FIFO control unit coordinates the operation of these two asynchronous
ports and issues the appropriate control signals. For proper operation of
the FIFO control unit, you must ensure that OCLK is frequency-locked to
ICLK.
The global control circuitry of the L64767 governs the entire data path
from an MPEG-2 input source, through the processing chain, and to the
final output from the device. Global control ensures that the output data
stream is continuous (no gaps between the symbols), assuming that the
incoming data rate is constant. The output clock OCLK of the L64767 is
externally derived from the input clock ICLK, and is kept in sync through
a phase-locked loop (PLL) module locked to the appropriate ICLK versus
OCLK ratio. Short term variations of frequency offset are handled by the
128-byte circular FIFO buffer. Other variations are controlled by the
external PLL module.
You can check for overrun errors using the FIFO collision detection
feature. This provides immediate output on a pin when a collision is
detected and sends an interrupt-generating event on the microprocessor
interface.
Microprocessor Interface
The L64767 has a bidirectional microprocessor interface that allows you
to write to and read back from the 14 internal registers. During normal
operation, the L64767 requires no interaction with the microprocessor.
However, you must configure all registers after a reset operation to
guarantee that the device will function properly.
The default operational mode of the L64767 is used for DVB-compliant
operation at 64 QAM, and for four-fold oversampling. However, the chip
supports modes of operation from 16 to 256 QAM.
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