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參數(shù)資料
| 型號： | L64767 |
| 廠商： | LSI CORP |
| 元件分類： | 消費家電 |
| 英文描述： | SMATV（Satellite Master Antenna Television） QAM Encoder(衛(wèi)星主天線電視正交振幅調(diào)制編碼器) |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP100 |
| 封裝： | MQUAD-100 |
| 文件頁數(shù)： | 14/32頁 |
| 文件大?。?/td> | 298K |
| 代理商： | L64767 |
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L64767 SMATV QAM Encoder
SYNCOK
SYNC Detection/Phase Monitoring
In internal sync mode, when this signal is HIGH, it
indicates a correct lock to the input sync sequence, and
the number of track steps required for synchronization is
fulfilled. If synchronization is forced by FSTARTIN pulses,
SYNCOK is constantly LOW.
Output
Control Signals
This section describes the control signals for the L64767.
OCLK
Output Processing Clock
This is a positive edge-triggered clock signal. The L64767
internally processes data (through the scrambler,
interleaver, and Reed-Solomon encoder) based on a
fraction of OCLK. Data outputs (I, Q, FSTARTOUT) are
referenced to OCLK. OCLK is independent of ICLK.
Input
PLL_OUT_CS PLL Current Source
This signal is a 4.5-mA charge pump output from the
phase/frequency detector. The comparator is frequency-
and phase-sensitive. This signal is normally 3-state Z
level, and drives positive and negative current as
required. Depending on the configuration, the current
source can be inverted.
Output
PLL_OUT_EX PLL Phase Sensitive EXOR Comparator
This signal is the output from the EXOR phase comparator.
Output
PLL_OUT_LO PLL Phase Sensitive Lock Detector
This signal is the output from the PLL lock detector.
Output
RESET
Reset
This is a level-sensitive data signal. It resets all internal
data paths. Reset timing is asynchronous to the device
clocks and does not interfere with the active clock edges
of ICLK and OCLK for reproducible output values. Reset
affects all the configuration registers and filter coefficients,
which must be downloaded again after reset.
Input
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