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參數(shù)資料
| 型號(hào)： | L64388 |
| 廠商： | LSI Corporation |
| 英文描述： | A General-Purpose,High-Performance Remote Access Communications Processor(通用的、高性能、遠(yuǎn)程訪問(wèn)通信處理器) |
| 中文描述： | 阿通用，高性能的遠(yuǎn)程訪問(wèn)通信處理器（通用的，高性能，遠(yuǎn)程訪問(wèn)通信處理器） |
| 文件頁(yè)數(shù)： | 5/12頁(yè) |
| 文件大?。?/td> | 129K |
| 代理商： | L64388 |
L64388 Remote Access Processor (RAP) Chip
5
write FIFOs. It provides a mailbox for PCI host to RAP messaging, and
provides hardware support for Intelligent I/O (I
2
O). It contains a
scatter/gather DMA and slave bridge to the local memory interface.
The Time Division Multiplexing (TDM) Serial Interface contains
independent transmit and receive TDM paths that operate at data rates
up to 20 MHz. This interface supports ISDN IOM-2, IDL, T1/E1, and
other TDM applications. It connects to up to four bidirectional serial
peripheral controllers for the IOM-2 M and C/I channels. It also connects
to four HDLC channels, which interconnect to the Serial WAN controllers.
The Serial Peripheral Interface (SPI) is a synchronous, bidirectional
interface that is used for ISDN transceiver management.
The Modem Interface supports two serial ports. The first serial port
interfaces to a line codec/DAA for analog modem applications. It
transfers data at rates up to 56 Kbits/s. The second serial port interfaces
to a voice codec for voice applications. The modem interface can
alternately route V.34 line and voice traffic to an ISDN B channel.
The Universal Asynchronous Receiver/Transmitter (UART) supports
start/stop traffic to line rates up to 1.5 Mbits/s. It provides hardware
support for automatic baud rate detection (ABRD).
The Timers block is comprised of four general-purpose 16-bit timers and
one 32-bit watchdog timer.
The Real-Time Clock (RTC) measures hours, minutes, and seconds with
0.04-second resolution.
The Local Memory Interface contains an integrated memory controller for
32-bit SDRAMs, 8-bit Flash PROMs, and peripheral devices. It also
contains an SDRAM refresh controller. It supports up to 64 Mbytes of
DRAM and 16 Mbytes of Flash memory.
The General-Purpose Interrupt/Control Interface (GPIO) provides 12
programmable, bidirectional pins used as additional interrupt inputs or
control outputs.
The TAP Controller supports boundary scan testing. The RAP chip
supports full scan/ATPG and IDDQ for factory testing.
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