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參數(shù)資料
| 型號： | L64388 |
| 廠商： | LSI Corporation |
| 英文描述： | A General-Purpose,High-Performance Remote Access Communications Processor(通用的、高性能、遠程訪問通信處理器) |
| 中文描述： | 阿通用，高性能的遠程訪問通信處理器（通用的，高性能，遠程訪問通信處理器） |
| 文件頁數(shù)： | 2/12頁 |
| 文件大?。?/td> | 129K |
| 代理商： | L64388 |
2
L64388 Remote Access Processor (RAP) Chip
Features
Functional Description
Figure 2 shows a functional block diagram of the RAP chip. This section
briefly describes the major blocks.
The CW4011 MiniRISC processor is based on a superscalar design,
performing at 160 native peak MIPS and 110 sustained MIPS at 80 MHz.
It connects to a 16-Kbyte instruction cache and an 8-Kbyte data cache.
The caches are either direct mapped or 2-way set associative. The
CW4011 uses big-endian data formatting. It provides a boot source
option, with the source coming either from a byte-wide EPROM or from
the PCI bus.
The multichannel DMA Controller (DMAC) provides seven full-duplex
channels. It performs burst memory operations at programmable lengths
of 1, 2, 4, or 8 words. The DMAC supports scatter gather and arbitrary
byte alignment.
Full-duplex, 10- and 100-Mbit/s
Ethernet LAN connection
HDLC-based WAN connectivity
at full-duplex data rates up to
52 Mbit/s (four ports)
Basic rate ISDN connectivity
MiniRISC
CW4011 MIPS
processor (160 MIPS peak,
110 MIPS sustained)
Real-Time Clock
Multichannel DMA controller
Multiprotocol hardware support
for HDLC, transparent, and
start/stop communications
32-bit, 33-MHz PCI interface
Integrated memory controller
Diagnostic/console port
Scalable connectivity using PCI
interface
ITU V.34 modem connectivity
Voice connectivity
G10
-p 3.3-V, 0.35-
μ
CMOS
fabrication technology
272-pin plastic ball grid array
(PBGA) package
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